RL1201LGO-711 データシートの表示（PDF） - PerkinElmer Inc
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RL1201LGO-711 Datasheet PDF : 8 Pages
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CMOS Spectroscopy Sensor
Table 1. Electrical Characteristics (25 C)
Sensor Characteristics (contd.)
Interference effects in the transparent
passivation layer over the diodes mod-
ulate this response. Since the details of
this modulation can vary from sensor
to sensor, the curve shown should be
taken only as representative of the short-
term wavelength-dependent variation
in quantum efficiency. The detail curve
was taken at 10 nm intervals while the
smoothed curve represents an average
over a bandwidth of approximately
100 nm.
Figure 4 shows the typical output
charge as a function of exposure at
650 nm wavelength for the 25 and 50 µm
pitch models. Exposure in nJ/cm2 is
calculated by multiplying the irradiance
in µW/cm2 by the integration time in
msec. The response is very linear up to
the saturation charge - 10 pC in 25 µm
models and 20 pC in the 50 µm models.
The dark current of an L-series sensor
at 25°C is typically 0.2 pA for the 25 µm
models or 0.4 pA for the 50 µm, doubling
for every 7°C increase in temperature.
See Table 2 for detailed electro-optical
characteristics.
Clock and Voltage
Requirements
Scanning is achieved by means of an
integrated shift register. The shift regis-
ter is driven by complementary square
wave clocks, Ø1 and Ø2. Table 1 gives
rise and fall times and crossover points
for these clock waveforms. The clock
amplitude should be equal to VDD – VSS.
With VDD = 5 V and VSS = 0 V, the clock
inputs will be HCMOS-compatible.
Since each photodiode is read out on a
negative transition of Ø2 (see Figure 6),
the frequency of the clock signal
should be set equal to the desired
video data rate.
The start pulse of similar amplitude to
the clocks is required to load the shift
register and initiate each readout period
(each scan of the array). The start pulse
is loaded when Ø2 is high; the start
signal is pulsed high for a minimum of
10 ns during one and only one Ø2 clock
high cycle. A timing diagram for the
start and clock signals is shown in
Figure 6. Caution: Ø1 and Ø2 clocks
need to be continuously applied to the
(All voltages measured with respect to VSUB)
Signal
Sym
Min
Typ
VDD
VDD guard
VSS
VSUB
Antiblooming drain
RL12xx
RL15xx
Start
Clock ø1, ø2
Reset gate 2
Antiblooming gate
RL12xx
RL15xx
Video bias
RL12xx
RL15xx
Reset drain 2
Clock rate
VDD
4.5
VDDG
-
VSS
-
VSUB
-
VABD
VABD
VSH High
VSL
Low
VH1, VH2 High
VL1, VL2 Low
-
VDD /2 - 0.1
VDD - 0.1
VDD - 0.1
VSS
VDD – 0.1
VSS
-
VHABG
VLABG
High VDD – 0.1
Low
VSS
VHABG High VDD – 0.1
VLABG Low
-3.0
VV
2
VV
4.5
VRD
-
-
0.001
5
VDD
0
0
-
-
-
-
-
-
VSS
-
-
-
-
VDD/2
VDD
VSS
-
Start rise time
tRS
-
10
Start fall time
tFS
-
10
Start pulse width
tPWS
10
-
ø1 Rise time
tR1
-
10
ø1 Fall time
tF1
-
10
ø2 Rise time
tR2
-
10
ø2 Fall time
tF2
-
10
Video delay time
tVD
-
20
Clock crossing
X1
0
-
X2
0
-
Capacitance ø1, ø2
at 5 V bias
RL1201
CC
RL1202
CC
RL1205
CC
RL1210
CC
RL1501
CC
RL1502
CC
RL1505
CC
Capacitance,
each video line at
at 2.5 V bias 1
-
9
-
50
-
77
-
154
-
30
-
48
-
93
RL1201
CV
RL1202
CV
RL1205
CV
RL1210
CV
Capacitance,
each video line
at 5.0 V bias 1
RL1501
CV
RL1502
CV
RL1505
CV
-
6.7
-
10.2
-
15.4
-
28.7
-
9.1
-
14
-
25
Notes:
1. Measured.
2. Clocking of Reset Gate may decrease dynamic range.
www.perkinelmer.com/opto
Max Units
5.5
V
-
V
-
V
-
V
VDD /2
V
VDD
V
VDD
V
VSS + 0.4 V
VDD
V
VSS + 0.4 V
-
V
VDD
V
VSS + 0.4 V
VDD
V
-2.0
V
VDD-2
V
5.5
V
-
V
1
MHz
50
ns
50
ns
-
ns
20
ns
20
ns
20
ns
20
ns
-
ns
50
%
50
%
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
-
pF
DSP-106.01C - 10/2001W Page 3
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