ADG467BRS データシートの表示（PDF） - Analog Devices

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ADG467BRS

Octal Channel Protectors

Analog Devices 

CIRCUIT INFORMATION

Figure 21 shows a simplified schematic of a channel protector

circuit. The circuit is made up of four MOS transistors—two

NMOS and two PMOS. One of the PMOS devices does not lie

directly in the signal path but is used to connect the source of

the second PMOS device to its backgate. This has the effect of

lowering the threshold voltage and thus increasing the input

signal range of the channel for normal operation. The source

and backgate of the NMOS devices are connected for the same

reason. During normal operation, the channel protectors have

an on resistance of 62 Ω typical. The channel protectors are very

low power devices, and even under fault conditions, the supply

current is limited to sub microampere levels. All transistors are

dielectrically isolated from each other using a trench isolation

method. This makes it impossible to latch up the channel protec-

tors. For further details, see the Trench Isolation section.

VSS

NMOS

PMOS

NMOS

PMOS

VDD

VSS

VDD

Figure 21. The Channel Protector Circuit

OVERVOLTAGE PROTECTION

When a fault condition occurs on the input of a channel protec-

tor, the voltage on the input has exceeded some threshold voltage

set by the supply rail voltages. The threshold voltages are related

to the supply rails as follows. For a positive overvoltage, the

threshold voltage is given by VDD − VTN, where VTN is the threshold

voltage of the NMOS transistor (1.5 V typical). In the case of a

negative overvoltage, the threshold voltage is given by VSS − VTP,

where VTP is the threshold voltage of the PMOS device (−1.5 V

typical). If the input voltage exceeds these threshold voltages,

ADG467

the output of the channel protector (no load) is clamped at these

threshold voltages. However, the channel protector output

clamps at a voltage value that is inside these thresholds if the

output is loaded. For example, with an output load of 1 kΩ, VDD =

15 V, and a positive overvoltage on the input, the output clamps

at VDD − VTN − ΔV = 15 V − 1.5 V − 0.6 V = 12.9 V, where ΔV is

due to an I × R voltage drop across the channels of the MOS

devices (see Figure 23). As can be seen from Figure 23, the current

during fault condition is determined by the load on the output

(that is, VCLAMP/RL). However, if the supplies are off, the fault

current is limited to the nano-ampere level.

Figure 22, Figure 24, and Figure 25 show the operating condi-

tions of the signal path transistors during various fault conditions.

Figure 22 shows how the channel protectors operate when a

positive overvoltage is applied to the channel protector.

VDD – VTN1

(+13.5V)

POSITIVE

NMOS

OVERVOLTAGE

(+20V)

SATURATED

PMOS

NON-

SATURATED

NMOS

NON-

SATURATED

VDD (+15V)

VSS (–15V)

VDD (+15V)

1VTN = NMOS THRESHOLD VOLTAGE (+1.5V).

Figure 22. Positive Overvoltage on the Channel Protector

The first NMOS transistor goes into a saturated mode of

operation as the voltage on its drain exceeds the gate voltage

(VDD) − the threshold voltage (VTN). This situation is shown in

Figure 23. The potential at the source of the NMOS device is

equal to VDD − VTN. The other MOS devices are in a nonsatu-

rated mode of operation.

VDx

(20V)

VG

VSx

(VDD = 15V)

(13.5V)

N+

N-CHANNEL N+

P+

OVERVOLTAGE

EFFECTIVE

OPERATION

SPACE CHARGE

(SATURATED)

REGION

(VO – VTN = 13.5V)

VT = 1.5V

P–

V

PMOS

NMOS

NONSATURATED

OPERATION

IOUT

Figure 23. Positive Overvoltages Operation of the Channel Protector

VCLAMP

RL

Rev. B | Page 9 of 16

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