LFSC3GA25E-7F900I データシートの表示（PDF） - Lattice Semiconductor
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LFSC3GA25E-7F900I Datasheet PDF : 237 Pages
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Lattice Semiconductor
Introduction
LatticeSC/M Family Data Sheet
Table 1-1. LatticeSC Family Selection Guide
Device
SC15
SC25
SC40
SC80
SC115
LUT4s (K)
15
25
40
80
115
sysMEM Blocks (18Kb)
56
104
216
308
424
Embedded Memory (Mbits)
1.03
1.92
3.98
5.68
7.8
Max. Distributed Memory (Mbits)
0.24
0.41
0.65
1.28
1.84
Number of 3.8Gbps SERDES (Max.)
8
16
16
32
32
DLLs
12
12
12
12
12
Analog PLLs
8
8
8
8
8
MACO Blocks
4
6
10
10
12
Package I/O/SERDES Combinations (1mm ball pitch)
256-ball fpBGA (17 x 17mm)
139/4
900-ball fpBGA (31 x 31mm)
300/8
378/8
1020-ball fcBGA (33 x 33mm)
476/16
562/16
1152-ball fcBGA (35 x 35mm)
604/16
660/16
660/16
1704-ball fcBGA (42.5 x 42.5mm)
904/32
942/32
Note: The information in this preliminary data sheet is by definition not final and subject to change. Please consult the Lat-
tice website and your local Lattice sales manager to ensure you have the latest information regarding the specifications for
these products as you make critical design decisions.
The LatticeSCM devices add MACO-enabled IP functionality to the base LatticeSC devices. Table 1-2 shows the
type and number of each pre-engineered IP core.
Table 1-2. LatticeSCM Family
Device
SCM15
SCM25
SCM40
SCM80 SCM115
flexiMAC Blocks
• 1GbE Mode
• 10GbE Mode
• PCI Express Mode
1
2
2
2
4
SPI4.2 Blocks
1
2
2
2
2
Memory Controller Blocks
• DDR/DDR2 DRAM Mode
• QDR II/II+ SRAM Mode
• RLDRAM I
• RLDRAM II CIO/SIO
1
2
2
2
2
Low Speed CDR Blocks
0
0
2
2
2
PCI Express LTSSM (PHY) Blocks
1
0
2
2
2
Note: See each IP core user’s guide for more information about support for specific LatticeSCM devices.
Introduction
The LatticeSC family of FPGA combines a high-performance FPGA fabric, high-speed SERDES, high-perfor-
mance I/Os and large embedded RAM in a single industry leading architecture. This FPGA family is fabricated in a
state of the art technology to provide one of the highest performing FPGAs in the industry.
This family of devices includes features to meet the needs of today’s communication network systems. These fea-
tures include SERDES with embedded advance PCS (Physical Coding sub-layer), up to 7.8 Mbits of sysMEM
embedded block RAM, dedicated logic to support system level standards such as RAPIDIO, HyperTransport,
SPI4.2, SFI-4, UTOPIA, XGMII and CSIX. The devices in this family feature clock multiply, divide and phase shift
PLLs, numerous DLLs and dynamic glitch free clock MUXs which are required in today’s high end system designs.
High speed, high bandwidth I/O make this family ideal for high throughput systems.
1-2
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