MSM9405MB データシートの表示（PDF） - Oki Electric Industry
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MSM9405MB Datasheet PDF : 30 Pages
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¡ Semiconductor
MSM9405
• DSR: DMA Mode Select Register (Address = 7h)
The DSR (DMA Mode Select Register) is used to select the DMA mode for the MSM9405. When
the system is reset, all bits of DSR are set to "0".
DSR DSR DSR DSR DSR DSR DSR DSR
7
6
5
4
3
2
1
0
DMA_EN ("1": DMA mode)
DMA_SL0 (DMA Select 0)
DMA_SL1 (DMA Select 1)
Not Used
DSR Bit
DSR[0]
DSR[1-2]
DSR[3-7]
Description
DMA_EN (DMA Mode Enable): This bit determines whether the DMA is to be used. The initial value
is set to "0".
When "1" is written to this bit, DSR[1-2] (DMA_SL0, DMA_SL1) setting is enabled and the
MSM9405 enters the DMA transfer standby mode. (DREQ is asserted when the DREQ assert
condition is met.)
If DMA_EN = "0", DSR[1-2] (DMA_SL0, DMA_SL1) setting is disabled and DMA transfer is not
performed. (DREQ is not asserted even if the DREQ assert condition is met.)
DMA_SL (DMA Select): These bits are used to select the method of interfacing with DMAC.
DMA_SL1
0
DMA_SL0
0
Function
DREQ becomes active low and DACK becomes active high.
When the RD signal becomes active while DACK is active,
the DMA read cycle (MemoryÆM9405) is selected. When
the WR signal becomes active while DACK is active, the
DMA write cycle (M9405ÆMemory) is selected. While
DACK is being asserted, address "0" (TDR/RDR) is
accessed regardless of the status of A0 to A3.
0
1
DREQ becomes active high and DACK becomes active low.
When the WR signal becomes active while DACK is active,
the DMA read cycle (MemoryÆM9405) is selected. When
the RD signal becomes active while DACK is active, the
DMA write cycle (M9405ÆMemory) is selected. While
DACK is being asserted, address "0" (TDR/RDR) is
accessed regardless of the status of A0 to A3.
1
0
DREQ becomes active low and DACK becomes active high.
DACK is disabled.
1
1
DREQ becomes active high and DACK becomes active low.
DACK is disabled.
These bits are not used.
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