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MSM9405 データシートの表示(PDF) - Oki Electric Industry

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MSM9405
OKI
Oki Electric Industry OKI
MSM9405 Datasheet PDF : 30 Pages
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¡ Semiconductor
MSM9405
EIR bit
EIR[0]
EIR[1]
EIR[2]
EIR[3]
EIR[4]
EIR[5]
EIR[6]
EIR[7]
Description
This bit works as FE_EV in SIR or Extended-SIR mode, as AS_EV in MIR mode, and as ECE_EV in
FIR mode. When the CPU reads the EIR contents, this bit is set to "0".
- FE_EV (Framing Error Event) (SIR mode/Extended-SIR mode): The bit is set to "1" when FE occurs.
- AS_EV (Abort Sequence Event) (MIR mode): The bit is set to "1" when an abort sequence is received.
- ECE_EV (Encode Error Event) (FIR mode): The bit is set to "1" when ECE occurs.
OE_EV (Overrun Error Event): When OE occurs, this bit is set to "1". When the CPU reads the EIR
contents, OE_EV is set to "0". The RSR characters are not transferred to the FIFO but overwritten.
CE_EV (CRC Error Event): When a CRC error occurs, this bit is set to "1". When the CPU reads the
EIR, this bit is set to "0". This bit is valid in either Extended-SIR, MIR, or FIR mode.
This bit is not used in SIR mode.
MLE_EV (Maximum Length Error Event): When MLE occurs, this bit is set to "1". When the CPU
reads the EIR, this bit is set to "0".
EOF_EV (End Of Frame Event): This bit is valid in either Extended-SIR, MIR, or FIR mode. When the
last byte in the frame's data field reaches the bottom of the FIFO in receiving mode, EOF_EV
is set to "1". When the CPU reads the EIR, this bit is set to "0". In SIR mode, this bit is not used.
RXH/T_EV (Receiver High-Data-Level/Timeout Event): When received data in the FIFO is at or above
the receiving threshold level or time-out occurs, RXH/T_EV is set to "1".
The condition for setting RXH/T_EV to "0" depends on the following two cases :
If received data in the FIFO is at or above the receiving threshold level : Received data is read.
When received data in the FIFO is below the threshold level, this bit is set to "0".
If time-out occurs :
After received data in the FIFO is read, this bit is set to "0".
TXL_EV (Transmitter Low-Data-Level Event): When sent data in the FIFO is below the sending
threshold level, this bit is set to "1". When sent data is written and sent data in the FIFO is at or
above the threshold level, this bit is set to "0".
TXE_EV (Transmitter Empty Event): When both FIFO and TSR are empty in sending mode, this bit
is set to "1". When the CPU reads the EIR, this bit is set to "0".
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