MTD800 データシートの表示（PDF） - Myson Century Inc

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MTD800

Integrated Fast Ethernet Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTD 800

(Preliminary)

Table 3.5 EEPROM Memory Map

Offset

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

|

3FH

40H

|

FFH

D15

D8 D7

D0

73H

CIS Pointer 1

CIS Pointer 3

MAX_LAT

SubSystem ID1

SubSystem Vendor ID1

Reserved

Ethernet Address 1

Ethernet Address 3

Ethernet Address 5

Reserved

Wake-up Lan Address 1

Wake-up Lan Address 3

Wake-up Lan Address 5

Reserved

CFG 2

Reserved

Last Word Pointer

CFG 0

CIS Pointer 0

CIS Pointer 2

MIN_GNT

SubSystem ID 0

SubSystem Vendor ID0

Reserved

Ethernet Address 0

Ethernet Address 2

Ethernet Address 4

Reserved

Wake-up Lan Address 0

Wake-up Lan Address 2

Wake-up Lan Address 4

Reserved

CFG 1

Reserved

Reserved for future use

Used for Card Bus Information Tuples

offset from

Mem Base

200H

202H

204H

206H

208H

20AH

20CH

20EH

210H

212H

214H

216H

218H

21AH

21CH

21EH

220H

222H

|

27EH

280H

|

3FFH

Note:

(1) The above figure shows the layout of serial EEPROM which takes the size of 4K bits.

(2) The low order byte of the first word contains the pointer to the last word of implementation specific area.

In this case, the value is “10H”. For different implementation, the area can be extended to “3FH’ in

maximum.

(3) The high order byte of the first word will be written as “73H” if the EEPROM has been programmed.

(4) The Card Bus CIS data are stored in the range addressed from 280H to 3FFH. The address is an offset

from Memory Base Address. The CIS can only be accessed from memory address space.

Table 3.6 Bit-Field Description of the Configuration words

Bit

Symbol

Description

Configuration Register 0

7

PMC Power Management Capability. Corresponding to Bit 4 of CFSR.

6

NDFA Not Defined Flow control Address. Corresponding to Bit 12 of RCR.

12/42

MTD800 Revision 0.0 07/20/1999

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