CY7C1041DV33 データシートの表示（PDF） - Cypress Semiconductor
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CY7C1041DV33 Datasheet PDF : 17 Pages
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CY7C1041DV33
AC Switching Characteristics
Over the Operating Range[9]
Parameter
Description
Read Cycle
tpower[11]
VCC(Typical) to the first access
tRC
Read cycle time
tAA
Address to data valid
tOHA
Data hold from address change
tACE
CE LOW to data valid
tDOE
OE LOW to data valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to low Z
OE HIGH to high Z[12, 13]
CE LOW to low Z[13]
CE HIGH to high Z[12, 13]
tPU
CE LOW to power-up
tPD
CE HIGH to power-down
tDBE
Byte enable to data valid
tLZBE
Byte enable to low Z
tHZBE
Byte disable to high Z
Write Cycle[14, 15]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to low Z[13]
WE LOW to high Z[12, 13]
Byte enable to end of write
–10
(Industrial)
Min
Max
–10
(Automotive-A) [10]
Min
Max
–12
(Automotive-E) [10]
Min
Max
Unit
100
–
100
–
100
–
μs
10
–
10
–
12
–
ns
–
10
–
10
–
12
ns
3
–
3
–
3
–
ns
–
10
–
10
–
12
ns
–
5
–
5
–
7
ns
0
–
0
–
0
–
ns
–
5
–
5
–
6
ns
3
–
3
–
3
–
ns
–
5
–
5
–
6
ns
0
–
0
–
0
–
ns
–
10
–
10
–
12
ns
–
5
–
5
–
7
ns
0
–
0
–
0
–
ns
–
6
–
6
–
6
ns
10
–
10
–
12
–
ns
7
–
7
–
8
–
ns
7
–
7
–
8
–
ns
0
–
0
–
0
–
ns
0
–
0
–
0
–
ns
7
–
7
–
8
–
ns
5
–
5
–
6
–
ns
0
–
0
–
0
–
ns
3
–
3
–
3
–
ns
–
5
–
5
–
6
ns
7
–
7
–
8
–
ns
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
10. Automotive product information is preliminary.
11. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
12. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads and Waveforms. Transition is measured when the outputs enter
a high impedance state.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given
device.
14. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
15. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05473 Rev. *I
Page 6 of 17
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