CY8CPLC20(2009) データシートの表示（PDF） - Cypress Semiconductor
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CY8CPLC20 Datasheet PDF : 44 Pages
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CY8CPLC20
2.1.1 The Digital System
The digital system contains 16 digital PSoC blocks. Each block
is an 8-bit resource that can be used alone, or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals called
user module references. Digital peripheral configurations
include:
■ PWMs (8 to 32 bit)
■ PWMs with Dead Band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity (up to four)
■ SPI master and slave (up to four each)
■ I2C slave and multi-master (one available as a System
Resource)
■ Cyclical Redundancy Checker and Generator (8 to 32 bit)
■ IrDA (up to four)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also enable signal multiplexing and perform logic opera-
tions. This configurability frees your designs from the constraints
of a fixed peripheral controller.
Figure 2-3. Digital System Block Diagram
Port 7
Port 5
Port 3
Port 1
Port 6
Port 4
Port 2
Port 0
DigitalClocks To SystemBus ToAnalog
FromCore
System
8
8
DIGITAL SYSTEM
Digital PSoCBlock Array
Row 0
4
DBB00 DBB01 DCB02 DCB03
4
Row 1
4
DBB10 DBB11 DCB12 DCB13
4
8
8
Row 2
4
DBB20 DBB21 DCB22 DCB23
4
Row 3
4
DBB30 DBB31 DCB32 DCB33
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 001-48325 Rev. *E
Page 8 of 44
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