CY8CPLC20(2009) データシートの表示（PDF） - Cypress Semiconductor
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CY8CPLC20 Datasheet PDF : 44 Pages
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CY8CPLC20
2. PSoC Core
The CY8CPLC20 is based on the Cypress PSoC® 1 archi-
tecture. The PSoC platform consists of many Programmable
System-on-chip Controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
and programmable interconnects. This architecture enables the
user to create customized peripheral configurations that match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable I/Os are included in a range of convenient pinouts
and packages.
The PSoC architecture, as shown in Figure 2-1., consists of four
main areas: PSoC Core, Digital System, Analog System, and
System Resources. Configurable global busing enables all the
device resources to be combined into a complete custom
system. The CY8CPLC20 family can have up to five I/O ports
that connect to the global digital and analog interconnects,
providing access to 16 digital blocks and 12 analog blocks.
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
Figure 2-1. PSoC Core
Port 7
Port 6
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
SYSTEM BUS
Global Digital Interconnect
Global Analog Interconnect
SRAM
2K
Interrupt
Controller
SROM Flash 32K PSoC CORE
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
Analog
Input
Muxing
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a 4 MIPS 8-bit Harvard architecture micropro-
cessor. The CPU uses an interrupt controller with 25 vectors, to
simplify programming of realtime embedded events. Program
execution is timed and protected using the included Sleep and
Watchdog timers (WDT).
Memory encompasses 32 KB of Flash for program storage, 2 KB
of SRAM for data storage, and up to 2 KB of EEPROM emulated
using Flash. Program Flash uses four protection levels on blocks
of 64 bytes, enabling customized software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 2.5
percent over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for the digital system use. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. When
operating the Powerline Transceiver (PLT) user module, the
ECO must be selected to ensure accurate protocol timing. The
clocks, together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, enabling great flexibility in external inter-
facing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
2.1 Programmable System Resources
Figure 2-2. Programmable System Resources
Powerline Network
Protocol
Physical Layer FSK
Modem
PLC Core
Embedded Application
Programmable
System Resources
Digital and Analog
Peripherals
Additional System
Resources
MAC, Decimator, I2C,
SPI, UART etc.
PSoC Core
Powerline Transceiver Packet
Digital
Clocks
Two
POR and LVD
Multiply Decimator I 2C
Accums.
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref.
Document Number: 001-48325 Rev. *E
Page 7 of 44
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