CY8CPLC20(2009) データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
一致するリスト
CY8CPLC20 Datasheet PDF : 44 Pages
| |||
CY8CPLC20
7. Pin Information
The CY8CPLC20 PLC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd and XRES are not capable of Digital I/O.
7.1 28-Pin Part Pinout
Table 7-1. 28-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Type
Digital Analog
I/O
I
Reserved
O
I/O
I
O
I/O
I/O
I
I/O
I
Reserved
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Input
O
I
Analog Ground
I/O
Reserved
Reserved
I/O
I/O
I
Power
Pin Name
Description
P0[7]
Analog Column Mux Input
RSVD
Reserved
FSK_OUT Analog FSK Output
P0[1]
Analog Column Mux Input
TX_SHUTD Output to disable PLC transmit
OWN
circuitry in receive mode
Logic ‘0’ - When the Modem is
transmitting
Logic ‘1’ - When the Modem is not
transmitting
P2[5]
P2[3]
Direct switched capacitor block
input
P2[1]
Direct switched capacitor block
input
RSVD
Reserved
P1[7]
I2C Serial Clock (SCL)
P1[5]
I2C Serial Data (SDA)
P1[3]
P1[1]
XTAL_STABILITY. Connect a
0.1 μF capacitor between the pin
and Vss.
Crystal (XTALin[2]), ISSP-SCLK[1],
I2C SCL
Vss
P1[0]
Ground connection.
Crystal (XTALout[2]),
ISSP-SDATA[1], I2C SDA
P1[2]
P1[4]
Optional External Clock Input
(EXTCLK[2])
P1[6]
XRES
Active high external reset with
internal pull down
RXCOMP_ Analog Output to external Low
OUT
Pass Filter Circuitry
RXCOMP_ Analog Input from the external Low
IN
Pass Filter Circuitry
AGND
Analog Ground
P2[6]
External Voltage Reference
(VREF)
RSVD
Reserved
RSVD
Reserved
P0[4]
Analog column mux input and
column output
FSK_IN
Analog FSK Input
Vdd
Supply Voltage
Figure 7-1. CY8CPLC20 28-Pin PLC Device
A , I , P0[7] 1
RSVD 2
FSK_OUT 3
A,I , P0[1] 4
TX_ SHUTDOWN 5
P2[5] 6
A,I , P2[3] 7
A ,I,P2[1] 8
RSVD 9
I2C SCL, P1[7] 10
I2C SDA, P1[5] 11
P1[3] 12
I2C SCL, XTALin, P1[1] 13
Vss 14
28
27
26
25
24
23
SSOP
22
21
20
19
18
17
16
15
Vdd
FSK_IN
P0[4] , A , IO
RSVD
RSVD
P2[6] , External VREF
AGND
RXCOMP_IN
RXCOMP_ OUT
XRES
P1[6]
P1[4] , EXTCLK
P1[2]
P1[0] , XTALout,I2C SDA
LEGEND: A = Analog, I = Input, O = Output., RSVD = Reserved (Should be left unconnected)
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for details.
2. When using the PLT user module, the external crystal is always required for protocol timing. For the FSK modem, either enable the PLL Mode or select the
external 24 MHz on P1[4]. Do not use the IMO.
Document Number: 001-48325 Rev. *E
Page 15 of 44
[+] Feedback
Share Link: 