CY8CPLC20(2009) データシートの表示（PDF） - Cypress Semiconductor

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CY8CPLC20
(Rev.:2009)

Powerline Communication Solution

Cypress Semiconductor 

CY8CPLC20

Table 8-2. Register Map Bank 1 Table: Configuration Space (continued)

Name

DBB01FN

Addr

(1,Hex)

Access

24

RW

Name

Addr

(1,Hex)

64

Access

Name

Addr

(1,Hex)

A4

DBB01IN

25

RW

65

A5

DBB01OU

26

RW

AMD_CR1

66

RW

A6

27

ALT_CR0

67

RW

A7

DCB02FN

28

RW

ALT_CR1

68

RW

A8

DCB02IN

29

RW

CLK_CR2

69

RW

A9

DCB02OU

2A

RW

6A

AA

2B

6B

AB

DCB03FN

2C

RW

TMP_DR0

6C

RW

AC

DCB03IN

2D

RW

TMP_DR1

6D

RW

AD

DCB03OU

2E

RW

TMP_DR2

6E

RW

AE

2F

TMP_DR3

6F

RW

AF

DBB10FN

30

RW

ACB00CR3

70

RW

RDI0RI

B0

DBB10IN

31

RW

ACB00CR0

71

RW

RDI0SYN

B1

DBB10OU

32

RW

ACB00CR1

72

RW

RDI0IS

B2

33

ACB00CR2

73

RW

RDI0LT0

B3

DBB11FN

34

RW

ACB01CR3

74

RW

RDI0LT1

B4

DBB11IN

35

RW

ACB01CR0

75

RW

RDI0RO0

B5

DBB11OU

36

RW

ACB01CR1

76

RW

RDI0RO1

B6

37

ACB01CR2

77

RW

B7

DCB12FN

38

RW

ACB02CR3

78

RW

RDI1RI

B8

DCB12IN

39

RW

ACB02CR0

79

RW

RDI1SYN

B9

DCB12OU

3A

RW

ACB02CR1

7A

RW

RDI1IS

BA

3B

ACB02CR2

7B

RW

RDI1LT0

BB

DCB13FN

3C

RW

ACB03CR3

7C

RW

RDI1LT1

BC

DCB13IN

3D

RW

ACB03CR0

7D

RW

RDI1RO0

BD

DCB13OU

3E

RW

ACB03CR1

7E

RW

RDI1RO1

BE

3F

ACB03CR2

7F

RW

BF

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

Access

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Name

VLT_CMP

DEC_CR2

IMO_TR

ILO_TR

BDG_TR

ECO_TR

CPU_F

FLS_PR1

CPU_SCR1

CPU_SCR0

Addr

(1,Hex)

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

Access

R

RW

W

W

RW

W

RL

RW

#

#

Document Number: 001-48325 Rev. *E

Page 21 of 44

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