MBM30LV0128 データシートの表示（PDF） - Fujitsu

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MBM30LV0128

128 M (16 M × 8) BIT NAND-type

Fujitsu 

MBM30LV0128

s SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT

The Program operation is implemented in page units while the Erase operation is carried out in block units.

Register

512

16

I/O0

I/O7

Read and Program operations

are executed through Register

Register = 1 page size

Memory Cell

Array

32 pages

→ 1 block

1) A page consists of (512 + 16) bytes;

- 512 bytes for main memory

- 16 bytes for redundancy or other use

8 I/O 2) A block consists of 16 pages; (16 K + 512) bytes.

3) Total device density =

528 bytes × 32 pages × 1024 blocks.

528

Figure 1 Schematic Cell Layout

Table 1 Addressing

First Cycle

Second Cycle

Third Cycle

I/O0

A0

A9

A17

I/O1

A1

A10

A18

I/O2

A2

A11

A19

I/O3

A3

A12

A20

I/O4

A4

A13

A21

I/O5

A5

A14

A22

I/O6

A6

A15

A23

I/O7

A7

A16

X*

A0 to A7 : column address

A9 to A23 : page address A14 to A23 : block address

A9 to A13 : Page address in block

(A8 is automatically set to “Low” or “High” by the “00h” command or the “01h” command inside the device.)

* : X = VIH or VIL

7

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