SBPH400-3 データシートの表示（PDF） - STMicroelectronics

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SBPH400-3

IEEE1394 3-Port 400Mbps Physical Layer

STMicroelectronics 

SBPH400-3

The fields in the Self-ID packet are derived as shown in Table 2.1.

Table 2.1

Field

phy_ID

L

gap_cnt

sp

rsv

c

pwr

p0, p1 p2

i

Self ID packet fields

Derived from

Comment

self-ID process or

set_PHY_ID packet

Link enabled register

physical node identifier

Logical AND of LPS signal and the Link_active register

Gap_Count register

Max_Phy_Speed

(reserved)

current value of Gap Count register

10b (S100, S200 and S400 capable)

00b

Contender register

Power class register

port status for port 0, 1 and

2 respectively

initiated reset

current value of C register

current value of Power class register

01 - not active (disabled, disconnected or suspended)

10 - active and connected to parent node

11 - active and connected to child node

set whenever the node initiated the current bus reset

2.7.3 Link_on packet

The SBPH400 will respond to a Link_on packet addressed to it received on the bus. The

packet has the following format:

Figure 2.3 Link_on packet format

01

phy_ID

0000

0000

0000

0000

logical inverse of first quadlet

0000

0000

If the logical AND of the LPS pin and the Link_active bit is zero, then the SBPH400 will

generate a 6.144 MHz signal on the LKON pin, until this logical value becomes 1. Otherwise

the packet is forwarded to the local link. Note that all Link_on packets received on the bus are

forwarded to the local link if it is active, whether or not the packets are addressed to the local

node.

2.7.4 PHY configuration packet

The SBPH400 will respond to every PHY configuration packet which it receives on the bus, or

from the link device for transmission on the bus. The packet has the format shown in Figure

2.4:

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