SBPH400-3 データシートの表示（PDF） - STMicroelectronics
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SBPH400-3 Datasheet PDF : 43 Pages
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SBPH400-3
2.8.7 Status transfer
A 4-bit status transfer of S[0:3] is initiated by the SBPH400 when any of the four status bits
S[0] to S[3] (as specified in Table 2.13) is set to 1. A 16-bit status transfer of s[0] to s[15] (as
specified in Table 2.13 is initiated by the link in response to a register read request from the
link device, or to indicate the node’s new phy_ID after a bus reset during the Self_ID process.
After the link interface is idle, a status transfer is initiated with the assertion of status (CTL[0:1]
= 10) condition by the SBPH400. The first two bits of status information (S[0:1]) are made
available on D[0:1]. The status condition is held on CTL[0:1] for the duration of transfer. The
SBPH400 ensures that there is at least one clock cycle between status transfers.
Table 2.13
Bit (S[n])
0
Status bits
Name
ArbitrationResetGap
1
SubactionGap
2
3
4-7
8-15
BusReset
PHY_Interrupt
Address
Data
Description
This bit indicates that the SBPH400 has detected that the
serial bus has been idle for an arbitration reset gap time (this
is defined in the IEEE 1394 standard). This bit is used by the
link device in the busy/retry state machine. This bit is reset
after the status transfer or when a transfer occurs on the bus.
This bit indicates that the SBPH400 has detected that the
serial bus has been idle for a subaction gap time (this is
defined in the IEEE 1394 standard). This bit is used by the link
device to detect the end of an isochronous cycle. This bit is
reset after a status transfer or when a transfer occurs on the
bus.
This bit indicates that the SBPH400 has entered the bus reset
state. This bit is reset after a status transfer
This bit is set whenever any of the interrupt-generating status
bits (Loop detect, Power fail, State time-out, Port event) is set
to 1. This bit is reset after a status transfer.
These bits indicate the address of the SBPH400 register
whose contents are being transferred to the link device
These bits provide the current value of SBPH400’s register.
Figure 2.11 Status transfer timing
SBPH400
CTL[0:1]
00
01
01
01
00
SBPH400
D[0:1]
00
S[0,1]
S[2,3]
S[14,15]
00
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