CA3256 データシートの表示（PDF） - Intersil
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CA3256 Datasheet PDF : 11 Pages
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CA3256
V- = -5V V+
10K (NOTE)
V-
V+
OFF SET
10K
ADJ.
15pF
IN 1
GEN
IN 2
IN 3
15
75Ω
17
75Ω
1
5
14
TG-1
BIAS
REG
TG-2
TG-3
V- +5V
10K
10K
1
RF
8
1K
1K
+
OUTPUT
AMP
VOUT = 2VP-P
9
510Ω
75Ω
V-
12
LED
1.2K
VLED
2
11
LED
1.2K
75Ω
IN 4
3
3
TG-4
10
LED
1.2K
75Ω
LLC
ENABLE
AND
4
2
CHAN 1-4
SELECT
IN 5
13
TG-5
LED
1.2K
NOTE: Adjust offset for voltage at
75Ω
AB
C
pin 9 equal to 0V with no AC signal
and one channel “ON”. Dynamic
6 ENABLE
16 18
7
4 clamping may be accomplished by
error current feedback to pin 8.
GND
FIGURE 5. TYPICAL APPLICATION WITH DC-COUPLED INPUT AND OUTPUT, AND OFFSET ADJUST. OUTPUT VOLTAGE IS
FIXED BY THE V+ AND V- RANGE. (DIP PINOUT)
+1
2VP-P
0
-1
10
10V
0
1µs/DIV.
FIGURE 6A. GATED OUTPUT FOR V+ = +12V ENABLE = HIGH, CONTROL B = C = LOW, CONTROL A = 10V PULSE. THE BURST
OUTPUT IS DELAYED ~ 400ns AT tON, tOFF.
10µs/DIV.
FIGURE 6B. STANDARD NTS COLOR BAR
10µs/DIV.
FIGURE 6C. UNIFORM STEP SIGNAL WITH 3.58MHz MODULATION
FIGURE 6. PERFORMANCE OF CIRCUIT IN FIGURE 5
8-9
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