M66281FP データシートの表示（PDF） - Renesas Electronics

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M66281FP

5120 × 8-Bit × 2 Line Memory

Renesas Electronics 

M66281FP

Notes on Reading of Written Data in Read Disable

When writing operation is performed at n cycle and n + 1 cycle on the writing side in the read disable period after n − 1

cycle on the reading side, output at n cycle and n + 1 cycle after read enable is invalid. For output at n + 2 cycle and

after, however, data written in the read disable period is to be output.

WCK

Dn

n − 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle n + 4 cycle n + 5 cycle n + 6 cycle n + 7 cycle

tDS tDH

(n − 1)

(n)

(n + 1)

(n + 2)

(n + 3)

(n + 4)

(n + 5)

(n + 6)

(n + 7)

RCK

n − 1 cycle

Disable cycle

n cycle n + 1 cycle n + 2 cycle

REB

Q0n

(Q1n)

tAC

tODIS

(n − 1)

HIGH-Z

tOEN

Invalid

Invalid

(n + 2)

WEB = "L"

WRESB = "H"

RRESB = "H"

REJ03F0254-0200 Rev.2.00 Sep 14, 2007

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