M66256FP データシートの表示（PDF） - Renesas Electronics

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M66256FP

5120 × 8-Bit Line Memory (FIFO)

Renesas Electronics 

M66256FP

Variable Length Delay Bits

1-line (5120 Bits) Delay

A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output

from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.

WCK

RCK

Cycle 0 Cycle 1 Cycle 2

Cycle 5120 Cycle 5121 Cycle 5122

Cycle 5118 Cycle 5119 (0')

(1')

(2')

tRESS tRESH

WRES

RRES

tDS tDH

tDS tDH

Dn

(0)

(1)

(2)

(5117)

(5118)

(5119)

(0')

(1')

(2')

(3')

5120 cycles

tAC

tOH

Qn

(0)

(1)

(2)

(3)

WE, RE = "L"

N-bit Delay Bit

(Making a reset at a cycle corresponding to delay length)

WCK

RCK

Cycle 0 Cycle 1 Cycle 2

Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3

Cycle n − 2 Cycle n − 1 (0')

(1')

(2')

(3')

tRESS tRESH

tRESS tRESH

WRES

RRES

tDS tDH

tDS tDH

Dn

(0)

(1)

(2)

(n − 3)

(n − 2)

(n − 1)

(0')

(1')

(2')

(3')

m cycles

tAC

tOH

Qn

(0)

(1)

(2)

(3)

WE, RE = "L"

m≥3

REJ03F0250-0200 Rev.2.00 Sep 14, 2007

Page 9 of 13

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