M66256FP
Shortest Read of Data "n" Written in Cycle n
(Cycle n − 1 on read side should be started after end of cycle n + 1 on write side)
When the start of cycle n − 1 on read side is earlier than the end of cycle n + 1 on write side, output Qn of cycle n
becomes invalid.
In the figure shown below, the read of cycle n − 1 is invalid.
WCK
Dn
RCK
Qn
Cycle n
Cycle n + 1
Cycle n + 2
Cycle n + 3
(n)
(n + 1)
(n + 2)
Cycle n − 2
Cycle n − 1
(n + 3)
Cycle n
Invalid
(n)
Longest Read of Data "n" Written in Cycle n: 1-line Delay
(Cycle n <1>* on read side should be started when cycle n <2>* on write is started)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle
<2>* overlap each other.
WCK
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
Dn
RCK
(n − 1) <1>*
(n) <1>*
Cycle n <0>*
(00) <2>*
Cycle 0 <1>*
(n − 1) <2>*
(n) <2>*
Cycle n <1>*
Qn
(n − 1) <0>*
(n) <0>*
Note: <0>*, <1>* and <2>* indicates a line value.
(0) <1>*
(n − 1) <1>*
(n) <1>*
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 11 of 13