EUA6011AQIT1 データシートの表示（PDF） - Eutech Microelectronics Inc

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EUA6011AQIT1

3-W Stereo Audio Power Amplifier with Advanced DC Volume Control

Eutech Microelectronics Inc 

EUA6011A

HP/LINE Operation

The HP/LINE input controls the internal input

multiplexer (MUX).Refer to the block diagram in Figure

30.This allows the device to switch between two separate

stereo inputs to the amplifier. For design flexibility, the

HP/LINE control is independent of the output mode, SE

or BTL, which is controlled by the aforementioned

SE/BTL pin. To allow the amplifier to switch from the

LINE inputs to the HP inputs when the output switches

from BTL mode to SE mode, simply connect the

SE/BTL control input to the HP/LINE input.

When this input is logic high, the RHPIN and LHPIN

inputs are selected .when this terminal is logic low, the

RLINEIN and LLINEIN inputs are selected. This operation

is also detailed in Table 4 and the trip levels for a logic low

(VIL) or logic high (VIH) can be found in the recommended

operation conditions table.

Shutdown Modes

The EUA6011A employs a shutdown mode of operation

designed to reduce supply current, IDD, to the absolute

minimum level during periods of nonuse for

battery-power conservation. The SHUTDOWN input

terminal should be held high during normal operation

when the amplifier is in use. Pulling SHUTDOWN low

causes the outputs to mute and the amplifier to enter a

low-current state, IDD<1µA. SHUTDOWN should never

be left unconnected because amplifier operation would be

unpredictable.

Table 3 . HP/LINE, SE/BTL , and Shutdown Function

Inputs

Amplifier State

HP/LINE SE/BTL SHUTDOWN INPUT OUTPUT

X

Low

Low

High

High

X

Low

High

Low

High

X= Do not care

Low

High

High

High

High

X

Mute

Line

BTL

Line

SE

HP

BTL

HP

SE

FADEOperation

For design flexibility, a fade mode is provided to slowly

ramp up the amplifier gain when coming out of shutdown

mode and conversely ramp the gain down when going into

shutdown. This mode provides a smooth transition

between the active and shutdown states and virtually

eliminates any pops or clicks on the outputs.

When the FADEinput is a logic low, the device is placed

into fade-on mode. A logic high on this pin places the

amplifier in the fade-off mode. The voltage trip levels for

a logic low (VIL) or logic high (VIH) can be found in the

recommended operating conditions table.

When a logic low is applied to the FADE pin and a logic

low is then applied on the SHUTDOWNpin, the channel

gain steps down from gain step to gain step at a rate of

two clock cycles per step. With a nominal internal clock

frequency of 58HZ,this equates to 34 ms (1/24 Hz) per

step. The gain steps down until the lowest gain step is

reached .The time it takes to reach this step depends on the

gain setting prior to placing the device in shutdown. For

example, if the amplifier is in the highest gain mode of

20dB, the time it takes to ramp down the channel gain is

1.05 seconds. This number is calculated by taking the

number of steps to reach the lowest gain from the highest

gain, or 31 steps , and multiplying by the time per step, or

34 ms.

After the channel gain is stepped down to the lowest gain,

the amplifier begins discharging the bypass capacitor from

the nominal voltage of VDD/2 to ground.

This time is dependent on the value of the bypass

capacitor. For a 0.47-µF capacitor that is used in the

application diagram in Figure 1, the time is approximately

500ms. This time scales linearly with the value of bypass

capacitor. For example, if a 1-µF capacitor is used for

bypass, the time period to discharge the capacitor to

ground is twice that of the 0.47-µF capacitor, or 1 second.

Figure 30 below is a waveform captured at the output

during the shutdown sequence when the part is in fade-on

mode. The gain is set to the highest level and the output is

at VDD when the amplifier is shut down.

When a logic high is placed on the SHUTDOWN pin

and the FADE pin is still held low, the device begins the

start-up process, the bypass capacitor will begin charging.

Once the bypass voltage reaches the final value of

VDD/2 ,the gain increases in2-dB steps from the lowest

gain level to the gain level set by the dc voltage applied to

the VOLUME, SEDIFF, and SEMAX pins.

In the fade-off mode, the amplifier stores the gain value

prior the staring the shutdown sequence. The output of the

amplifier immediately drops to VDD/2 and the bypass

capacitor begins a smooth discharge to ground When

shutdown is released, the bypass capacitor charges up to

VDD/2 and the channel gain returns immediately to the

value stored in memory. Figure 31 below is a waveform

captured at the output during the shutdown sequence when

DS6011A Ver 1.0 Mar. 2006

15

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