AX88140A データシートの表示（PDF） - Unspecified

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AX88140A

Fast Ethernet MAC Controller

Unspecified 

AX88140A

MRCLK/SYMRCLK

I

128

MRXD<3>/SYMRXD<3>

I

132,

MRXD<2>/SYMRXD<2>

131,

MRXD<1>/SYMRXD<1>

130,

MRXD<0>/SYMRXD<0>

129

MTCLK/SYMTCLK

I

137

MTXD<3>/SYMTXD<3>

O

145,

MTXD<2>/SYMTXD<2>

144,

MTXD<1>/SYMTXD<1>

141,

MTXD<0>/SYMTXD<0>

140

MTXEN/SYMTXEN

O

139

RCV_MATCH

O

136

SD

SRL_CLSN

I

123

I

148

SRL_RCLK

SRL_RXD

SRL_RXEN

I

151

I

149

I

150

SRL_TCLK

SRL_TXD

SRL_TXEN

SYMRXD <4>

SYMTXD<4>

I

153

O

152

O

154

I

133

O

146

PRELIMINARY

114

Supports either the 25-MHZ or 2.5-MHZ receive

clock. This clock is recovered by the PHY.

118,

Four parallel receive data lines When MII mode is

117,

selected. This data is driven by an external PHY that

116,

attached the media and should be synchronized with

115

the MRCLK/SYMRCLK signal.

123

Supports the 25-MHZ or 2.5-MHZ transmit clock

supplied by the external physical layer medium

dependent (PMD) device. This clock should always

be active.

131,

Four parallel transmit data lines. This data is

130,

synchronized to the assertion of the

127,

MTCLK/SYMTCLK signal and is latched by the

126

external PHY on the rising edge of the

MTCLK/SYMTCLK signal.

125

Transmit enable signals that the transmit is active to

an external PHY device. In PCS mode (REG6<23>),

This signal reflects the transmit activity of the MAC

sub-layer.

122

Receive match indication is asserted when a received

packet has passed address recognition.

Receive match indication is asserted when a received

packet has passed address recognition.

109

Signal detect indication supplied by an external

physical layer medium dependent (PMD) device.

134

Collision detect signals a collision occurrence on the

Ethernet cable to the AX88140A. It may be asserted

and deasserted asynchronously by the external

ENDEC to the receive clock.

137

Receive clock carries the recovered receive clock

supplied by an external ENDEC. during idle periods,

SRL_RCLK may be inactive.

135

Receive data carries the input receive data from the

external ENDEC. The incoming data should be

synchronous with the SRL_RCLK signal.

136

Receive enable signals activity on the Ethernet cable

to the AX88140A. It is asserted when receive data is

present on the Ethernet cable and is deasserted at the

end of a frame. It may be asserted and deasserted

asynchronously to the receive clock (SRL_RCLK) by

the external ENDEC.

139

Transmit clock carries the transmit clock supplied by

an external ENDEC. This clock must always be

active (even during reset).

138

Transmit data carries the serial output data from the

AX88140A. This data is synchronized to the

SRL_TCLK signal.

140

Transmit enable signals an external ENDEC That the

AX88140A transmit is in progress.

119

Receive data, together with the four receive lines

MII/SYM_RXD<3:0>, Provide five parallel lines of

data in symbol from for use in PCS mode

(100BASE-T, REG6<23). This data is synchronized

on the rising edge of the MTCLK/SYMTCLK signal.

132

Transmit data, together with the our transmit lines

MII/SYM_TXD<3:0>,provide five parallel lines of

data in symbol form for use in PCS mode

(100BASE-T, REG6<23>). This data is synchronized

on the rising edge of the MII/SYM_TCLK signal.

Tab - 3 MII/SYM/SRL interface signals group

15

ASIX ELECTRONICS CORPORATION

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