AX88140A データシートの表示（PDF） - Unspecified

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コンポーネント説明

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AX88140A

Fast Ethernet MAC Controller

Unspecified 

AX88140A

PAR

I/O

53

PCI_CLK

I

7

PERR#

I/O

51

REQ#

O

10

RST#

I

4

SERR#

I/O

52

STOP#

I/O

49

TRDY#

I/O

47

PRELIMINARY

IRDY# to indicate that it is ready to accept data.

47

Parity is an even parity bit for the AD<31:0> AD and CBE#<3:0>.

During address and data phases, parity is calculated on all the

AD<31:0> AND CBE#<3:0>lines whether or not any of these

lines carry meaningful information.

5

The clock provides the timing for the AX88140A related PCI bus

transactions. All the bus signals are sampled on the rising edge of

PCI_CLK. The clock frequency range is between 21MHZ and

33MHZ.

45

Parity error asserts when a data parity error is detected. When the

AX88140A is the bus master it monitor PERR# to see if the target

report a data parity error., when the AX88140A is the bus target

and a parity error is detected, the AX88140A asserts PERR#. This

pin must be pulled up by an external resistor.

8

Bus request is asserted by the AX88140A to indicate to the bus

arbiter that it wants to use the bus.

2

Resets the AX88140A to its initial state. This signal must be

asserted for at least 10 active PCI clock cycles. When is the reset

state, all PCI output pins are put into tri-state and all PCI o/d

signals are floated.

46

System Error is used by AX88140A to report address parity Error.

This pin must be pulled up by an external resistor.

43

Stop indicator indicates that the current target is requesting the bus

master to stop the current transaction. The AX88140A responds to

the assertion of STOP# when it is the bus master, and stop the

current transaction.

41

Target ready indicates the target ability to complete the current data

phase of the transaction.

A data phase is completed on any clock when both TRDY# and

IRDY# are asserted. Wait cycles are inserted until both IRDY#

and TRDY# are asserted together. When the AX88140A is the bus

master, target ready is asserted by the bus slave on the read

operation, indicating that valid data is present on the ad lines.

During a write cycle, it indicates that the target is prepared to

accept data.

Tab - 1 PCI interface group

13

ASIX ELECTRONICS CORPORATION

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