AD12400 データシートの表示（PDF） - Analog Devices
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AD12400 Datasheet PDF : 24 Pages
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AD12400
Figure 20 displays the application of this relationship to a full-
scale, single-tone input signal on the AD12400, where the DNL
was assumed to be 0.4 LSB, and the input noise was assumed to
be 0.8 LSBrms. The vertical marker at 0.4 ps displays the SNR at
the jitter level present in the AD12400 evaluation system,
including the jitter associated with the AD12400 itself.
65
AIN = 10MHz
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63
AIN = 65MHz
62
AIN = 128MHz
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60
59
AIN = 180MHz
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57
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
APERTURE JITTER (ps rms)
Figure 20. SNR vs. Aperture Jitter
In addition to jitter, the harmonic content of the single-ended
sine wave clock sources must be controlled. The clock source
used in the test and calibration process has an harmonic
performance that is better than 60 dBc. Also, when using PECL
or other square-wave clock sources, unstable behavior, such as
overshoot and ringing, can affect phase matching and degrade
the image spur performance.
DIGITAL OUTPUTS
The AD12400’s digital postprocessing circuit provides two
parallel, 12-bit, 200 MSPS data output buses. By providing two
output busses that operate at one half the conversion rate, the
AD12400 eliminates the need for large, expensive, high power
demultiplexing circuits. The output data format is twos
complement, maintaining the standard set by other high speed
ADCs, such as the AD9430 and AD6645. Data-ready signals are
provided for facilitating proper timing in the data capture
circuit. The digital postprocessing circuit can be configured to
provide alternate data output formats.
POWER SUPPLIES
The AD12400 requires three different supply voltages: a 1.5 V
supply for the digital postprocessing circuit, a 3.3 V supply to
facilitate digital I/O through the system, and a 3.8 V supply for
the analog conversion and clock distribution circuits. The
AD12400 incorporates two key features that result in solid
PSRR performance. First, on-board linear regulators are used to
provide an extra level of power supply rejection for the analog
circuits. The linear regulator used to supply the ADCs provides
an additional 60 dB of rejection at 100 kHz. Second, in order to
address higher frequency noise (where the linear regulators’
rejection degrades), the AD12400 incorporates high quality
ceramic decoupling capacitors.
While this product has been designed to provide good PSRR
performance, system designers need to be aware of the risks
associated with switching power supplies and consider using
linear regulators in their high speed ADC systems. Switching
power supplies typically produces both conducted and radiated
energy that result in common-/differential-mode EMI currents.
Any system that requires 12-bit performance has very little
room for errors associated with power supply EMI. For exam-
ple, a system goal of 74 dB dynamic range performance on the
AD12400 requires noise currents that are less than 4.5 μA and
noise voltages of less than 225 μV in the analog input path.
START-UP AND RESET
The AD12400’s FPGA configuration is stored in the on-board
EPROM and loaded into the FPGA when power is applied to
the device. The RESET pin (active low) allows the user to reload
the FPGA in case of a low digital supply voltage condition or a
power supply glitch. Pulling the RESET pin low pulls the data
ready and output bits high until the FPGA is reloaded. The
RESET pin should remain low for a minimum of 200 ns. On the
rising edge of the reset pulse, the AD12400 starts loading the
configuration into the FPGA. The reload process requires a
maximum of 600 ms to complete. Valid signals on the data
ready pins indicate the reset process is complete. Also, system
designers must be aware of the thermal conditions of the
AD12400 at startup. If large thermal imbalances are present,
the AD12400 may require additional time to stabilize before
providing specified image spur performance.
LEAD/LAG
The LEAD/LAG pin is used to synchronize the collection of
data into external buffer memories. The LEAD/LAG pin can be
applied synchronously or asynchronously to the AD12400. If
applied asynchronously, LEAD/LAG must be held low for a
minimum of 5 ns to ensure correct operation. The function
shuts off DRA and DRB until the LEAD/LAG pin is set high
again. DRA and DRB resumes on the next valid DRA after
LEAD/LAG is released. If this feature is not required, tie this
pin to 3.3 V through a 3.74 kΩ.
THERMAL CONSIDERATIONS
The module is rated to operate over a case temperature of 0°C
to 60°C. To maintain the tight channel matching and reliability
of the AD12400, care must be taken to assure that proper
thermal and mechanical considerations have been made and
addressed to ensure case temperature is kept within this range.
Each application requires evaluation of the thermal manage-
ment as applicable to the system design. This section provides
information that should be used in the evaluation of the
AD12400’s thermal management for each specific use.
Rev. A | Page 14 of 24
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