AD12400 データシートの表示（PDF） - Analog Devices
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AD12400 Datasheet PDF : 24 Pages
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AD12400
THEORY OF OPERATION
The AD12400 uses two high speed, 12-bit ADCs in a time-
interleaved configuration to double the sample rate, while
maintaining a high level of dynamic range performance. The
digital output of each ADC channel is calibrated using a
proprietary digital postprocessing technique, Advanced Filter
Bank (AFB). AFB is implemented using a state-of-the-art field
programmable gate array (FPGA) and provides a wide
bandwidth and wide temperature match for any gain, phase,
and clock timing errors between each ADC channel.
TIME-INTERLEAVING ADCS
When two ADCs are time-interleaved, gain and/or phase
mismatches between each channel produce an image spur at
fs/2 − fAIN and an offset spur as shown in Figure 18. These
mismatches can be the result of any combination of device
tolerance, temperature, and frequency deviations.
0
–10
1
–20
–30
IMAGE SPUR
–40
X
–50
OFFSET SPUR
–60
–70
–80
–90
–100
2
3
5
4
N
6
–110
–120
0 20 40 60 80 100 120 140 160 180 200
.
FREQUENCY (MHz)
Figure 18. Image Spur due to Mismatches Between Two Interleaved ADCs
(No AFB Digital Postprocessing)
Figure 19 shows the performance of a similar converter with
on-board AFB postprocessing implemented. The –44 dBFS
image spur has been reduced to –77 dBFS and, as a result, the
dynamic range of this time-interleaved ADC is no longer
limited by the channel matching.
0
1
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
IMAGE SPUR
OFFSET SPUR
3
X
2
N
5
4
6
–110
–120
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 19. AD12400 with AFB Digital Postprocessing
The relationship between image spur and channel mismatches
is captured in Table 7 for specific conditions.
Table 7. Image Spur vs. Channel Mismatch
Gain Error (%)
1
0.25
0.2
0.025
Aperture Delay Error (ps)
15
2.7
1.1
0.5
Image Spur
(dBc)
–40
–54
–62
–70
For a more detailed description of time-interleaving in ADCs
and a design example using the AD12400, refer to “Advanced
Digital Post-Processing Techniques Enhance Performance in
Time Interleaved ADC Systems,” published in the August, 2003
edition of Analog Dialogue. This article can be found at
http://www.analog.com/analogDialogue.
ANALOG INPUT
The AD12400 analog input is ac-coupled using a proprietary
transformer front-end circuit that provides 1 dB of gain flatness
over the first Nyquist zone and a –3 dB bandwidth of 450 MHz.
This front-end circuit provides a VSWR of 1.5 (50 Ω) over the
first Nyquist zone, and the typical full-scale input is 3.2 V p-p.
The Mini-Circuits® HELA-10 amplifier module can be used to
drive the input at these power levels.
CLOCK INPUT
The AD12400 requires a 400 MSPS encode that is divided by 2
and distributed to each ADC channel, 180° out of phase from
each other. Internal ac coupling and bias networks provide the
framework for flexible clock input requirements that include
single-ended sine wave, single-ended PECL, and differential
PECL. While the AD12400 is tested and calibrated using a
single-ended sine wave, properly designed PECL circuits that
provide fast slew rates (>1 V/ns) and minimize ringing result in
comparable dynamic range performance.
Aperture jitter and harmonic content are two major factors to
consider when designing the input clock circuit for the
AD12400. The relationship between aperture jitter and SNR can
be characterized using the following equation. The equation
assumes a full-scale, single-tone input signal.
SNR =
( ) ⎡
− 20log⎢⎢
⎢⎣
20π ×
fA
× 0t JRMS
2
+
1
1.5
×
⎜⎝⎛
1+
2N
ε
⎟⎠⎞2
+
⎜⎜⎝⎛ 2
2
× VNOISErms
2N
⎟⎟⎠⎞2
⎤
⎥
⎥
⎥⎦
where:
fA = input frequency.
tJRMS = aperture jitter.
N = ADC resolution (bits).
ε = ADCDNL (LSB).
VNOISE = ADC input noise (LSBrms).
Rev. A | Page 13 of 24
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