AD12400(Rev0) データシートの表示（PDF） - Analog Devices
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AD12400 Datasheet PDF : 28 Pages
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AD12400
Table 4. Output Coding (Twos Complement)
Code
AIN (V)
Digital Output
4095
+1.6
0111 1111 1111
.
.
.
.
.
.
.
.
.
2048
0
0000 0000 0000
2047
−0.000781
1111 1111 1111
.
.
.
.
.
.
0
−1.6
1000 0000 0000
Table 5. Option Pin List With Necessary Associated Circuitry
Active
High or
Pin Name Low
Logic
Level
Type
Default
Level
Associated
Circuitry
Within Part
RESET
Low
LVTTL High
3.74 kΩ Pull-Up
LEAD/LAG Low
LVTTL Low
10 kΩ − 60 kΩ
Pull-Down
ENCODE
ENCODE
3.3V
100Ω
3.3V
100Ω
100Ω
PECL
DRIVER
100Ω
Figure 2. Encode Equivalent Circuit
N–1 N N+1
N+2
N+3
tEL
tEH
ENCODE
400MHZ
DATA OUT A
1/fS
40 CLOCK CYCLES
N – 40 N – 39
*
N
N+2
N+4
N+6
N+8
DRA
DRA
DATA OUT B
N+1
N+3
*
N+5
N+7
DRB
DRB
LEAD LAG
*DATA LOST DUE TO ASSERTION OF LEAD/LAG. LATENCY OF 40 ENCODE CLOCK CYCLES BEFORE DATA VALID.
NOTES:
1 IF A SINGLE-ENDED SINEWAVE IS USED FOR ENCODE, USE THE "ZERO CROSSING" POINT (AC-COUPLED) AS THE 50%
POINT AND APPLY THE SAME TIMING INFORMATION.
2 THE LEAD/LAG PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES. THE
LEAD/LAG PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12400. IF APPLIED
ASYNCHRONOUSLY, LEAD/LAG MUST BE HELD HIGH FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION. THE
FUNCTION WILL SHUT OFF DRA AND DRB UNTIL THE LEAD/LAG PIN IS RELEASED. DRA AND DRB WILL RESUME ON THE
NEXT VALID DRA AFTER LEAD/LAG IS RELEASED.
Figure 3. Timing Diagram
tPD
ENC
ENC
DATA OUT
DR
DR
tV
Figure 4. Highlighted Timing Diagram
Rev. 0 | Page 7 of 28
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