PM7350 データシートの表示（PDF） - PMC-Sierra
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PM7350 Datasheet PDF : 241 Pages
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RELEASED
DATA SHEET
PMC-1980581
ISSUE 5
PM7350 S/UNI-DUPLEX
DUAL SERIAL LINK PHY MULTIPLEXER
The S/UNI-VORTEX resides on the core card and terminates up to 8 LVDS links
connected to 8 S/UNI-DUPLEX devices. The S/UNI-VORTEX implements the
second stage of multiplexing. More than one S/UNI-VORTEX will be required if
more than 8 links are required – as will be the case for a system with more than
8 line cards. The S/UNI-VORTEX device(s) share a high speed parallel bus with
the core card’s traffic management and OA&M layers, as implemented by
devices such as PMC-Sierra’s S/UNI-APEX and the S/UNI-ATLAS.
Some applications use framer or modem devices without integrated I.432
processing1 normally support a clock and data interface, and rely on external
circuitry to detect and generate ATM cell framing and overhead. To support
these applications, the S/UNI-DUPLEX provides a clock and data mode2. In this
mode, the input/output pins that normally interface to the Utopia bus are
configured to support up to 16 clock and data serial interfaces. This type of line
card is shown in Fig. 3. The I.432 processing is transparent to the far end
device, which implies that a single S/UNI-VORTEX can simultaneously interface
to line cards that implement the Utopia bus and to line cards that use clock and
data interfaces.
Fig. 3 Clock and Data PHY Interface
Line Card
Rx Clock
Modem #1
Rx Data
Tx Clock
Tx Data
S/UNI-
DUPLEX
4-wire
LVDS
Modem #16
Some PHY devices provide a 3-line interface consisting of clock, data, and
overhead indication. For these PHYs external circuitry can be used to adapt to
the S/UNI-DUPLEX’s 2-line interface.
1 Cell delineation, payload scrambling-descrambling, idle cell generation/discard, etc..
2 Either Utopia mode or clock and data mode can be selected, but not both at once.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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