PM7350 データシートの表示（PDF） - PMC-Sierra

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PM7350

DUAL SERIAL LINK PHY MULTIPLEXER

PMC-Sierra 

RELEASED

DATA SHEET

PMC-1980581

ISSUE 5

PM7350 S/UNI-DUPLEX

DUAL SERIAL LINK PHY MULTIPLEXER

• Cell read/write to both LVDS links available through the processor port.

Provides optional hardware assisted CRC32 calculation across cells to

support an embedded inter-processor communication channel across the

LVDS links.

• Requires no external memories.

• Standard 5 pin P1149.1 JTAG test port.

• Low-power, 3.3V CMOS technology.

• 160-pin high-performance plastic ball grid array (PBGA) package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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