ZR36067 データシートの表示（PDF） - Unspecified

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ZR36067

AV PCI CONTROLLER

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AV PCI CONTROLLER

13.29 JPEG Codec Guest ID

This register contains the ZR36060 (or ZR36050) Guest ID for

the JPEG START (or GO command) cycle.

Address Offset: 0x124

Bit

31 :7

6:4

3

2:0

Type

R

RW

R

RW

Mod

jpg

jpg

Description

Reserved, Returns zero.

JPEGuestID - JPEG Codec Guest ID.

These three bits define the guest port to

which the ZR36060 (or ZR36050) is connect-

ed, in order to perform the JPEG START (or

GO command) cycle.

Default value is 100b

Reserved, Returns zero.

JPEGuestReg - JPEG Codec Register.

These three bits define the guest register for

the JPEG GO command to a ZR36050. Not

used with ZR36060.

Default value is 000b

13.30 GuestBus Control Register (II)

This register contains the timing parameters of an additional 4

guests (the first 4 guests’ parameters are defined in 13.12

“General Purpose Pins and GuestBus Control Register (I)”).

Address Offset: 0x12C

Bit

31 : 16

15 : 14

13 :12

11 : 8

7:4

3:0

Type

R

RW

RW

RW

RW

RW

Mod

res

res

res

res

res

Description

Reserved, Returns zero.

Duration time for guest 7:

00b - Tdur7 = 3 PCI clocks (default value),

01b - Tdur7 = 4 PCI clocks,

10b - Tdur7 = 12 PCI clocks,

11b - Tdur7 = 15 PCI clocks.

Recovery time for guest 7:

00b - Trec7 = 3 PCI clocks (default value),

01b - Trec7 = 4 PCI clocks,

10b - Trec7 = 12 PCI clocks,

11b - Trec7 = 15 PCI clocks.

Duration and recovery time of guest 6

(same structure as defined for guest 7 above)

Duration and recovery time of guest 5

(same structure as defined for guest 7 above)

Duration and recovery time of guest 4

(same structure as defined for guest 7 above)

13.31 “Still Transfer” Register

This register is used for data and control in Still Image Compres-

sion or Decompression.

Address Offset: 0x300

Bit

31/7

31 : 0

Type

R

RW

Mod

all

all

Description

Still_Bsy - Still Transfer Busy indication bit.

The bit indicates to the host whether the “Still

Transfer” register is available to write the next

pixel in Still Image Compression mode.

When this bit is ‘0’, the register is available.

The bit location depends on the

Still_LitEndian configuration bit in the JPEG

Mode and Control register. If Little Endian

format was selected then the bit location is

31. If Gib Endian format was selected then

the bit location is 7.

When Still Image Compression mode is

selected (and after P_reset was de-assert-

ed), the bit is ‘0’. After the host writes a pixel,

the bit is set to ‘1’. The bit remains ‘1’ until the

pixel is synchronized to the video clock and

going to be driven out from the ZR36067

video port. Then when the register is avail-

able again, the bit is reset to ‘0’.

When Still Image Decompression mode is

selected (and after P_reset was de-assert-

ed), the bit is ‘1’. After the ZR36067 fetches a

new pixel, and the pixel is ready for the host

to read it, the bit is reset to ‘0’. It is set to ‘1’

again after the pixel was read.

‘1’ - The register is not available.

‘0’ - The register is available.

Default value is ‘0’.

Still Transfer Pixel register. The byte order

(RGB or BGR) is defined by the

Still_LitEndian configuration bit in the JPEG

Mode and Control register.

If Little Endian format was selected, the byte

order is:

R7..0 on bits 23..16.

G7..0 on bits 15..8.

B7..0 on bits7..0.

If Gib Endian format was selected, the byte

order is:

R7..0 on bits 15..8.

G7..0 on bits 23..16.

B7..0 on bits 31..24.

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