XRT84L38 データシートの表示（PDF） - Exar Corporation
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XRT84L38 Datasheet PDF : 453 Pages
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REV. 1.0.1
TRANSMIT SERIAL DATA INPUT
(Framer Channel Number indicated by _n)
XRT84L38
OCTAL T1/E1/J1 FRAMER
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
TxInClk_0
TxInClk_1
TxInClk_2
TxInClk_3
TxInClk_4
TxInClk_5
TxInClk_6
TxInClk_7
C6
B13
A22
F26
AC26
AF21
AF10
AE6
I Transmit Input Clock Signal -- Transmit Framer _n
If TxMUXEN ≠ 0 or TxIMODE[1:0] ≠ 00 in Transmit interface control register,
Transmit back-plane interface of Framer_n is operating at a high-speed mode.
This pin will function as an input clock signal for the high-speed Transmit back-
plane interface.
DS1 Mode:
Transmit Back-plane Interface-MVIP, 2.048 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 01 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 2.048
Mbit/s. The TxInClk_n signal will be an Input clock signal running at 2.048
MHz.
Transmit Back-plane Interface-4.096 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 10 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 4.096
Mbit/s. The TxInClk_n signal will be an Input clock signal running at 4.096
MHz.
Transmit Back-plane Interface-8.192 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 11 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 8.192
Mbit/s. The TxInClk_n signal will be an Input clock signal running at 8.192
MHz.
Transmit Back-plane Interface-Multiplexed at 12.352 MHz Clock Mode
If TxMUXEN = 1 and TxIMODE[1:0] = 00 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking multiplexed data at a rate
of 12.352 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals
running at 12.352 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not
required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and
latched into Transmit back-plane interface using clock edge of TxInClk_0 via
TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-
plexed and latched into Transmit back-plane interface using clock edge of
TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-
plexed into 8 channels from the serial inputs of Channel 0 and 4.
Transmit Back-plane Interface-Multiplexed at 16.384 MHz Clock Mode
If TxMUXEN = 1 and TxIMODE[1:0] = 01 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking multiplexed data at a rate
of 16.384 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals
running at 16.384 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not
required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and
latched into Transmit back-plane interface using clock edge of TxInClk_0 via
TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-
plexed and latched into Transmit back-plane interface using clock edge of
TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-
plexed into 8 channels from the serial inputs of Channel 0 and 4.
Transmit Back-plane Interface-HMVIP, 16.384 MHz Clock Mode
If TxMUXEN = 1 and TxIMODE[1:0] = 10 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking multiplexed data at a rate
of 16.384 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals
running at 16.384 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not
required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and
latched into Transmit back-plane interface using clock edge of TxInClk_0 via
TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-
plexed and latched into Transmit back-plane interface using clock edge of
TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-
plexed into 8 channels from the serial inputs of Channel 0 and 4.
9
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