HFA3860B データシートの表示（PDF） - Intersil
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HFA3860B Datasheet PDF : 40 Pages
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HFA3860B
TABLE 5. TEST MODES (Continued)
MODE DESCRIPTION TEST_CLK
TEST (7:0)
11
Reserved
Reserved Factory Test Only
12
A/D Cal Test A/D Cal CLK A/DCal, ED, A/DCal
Mode
Disable, ADCal (4:0)
13 Correlator I High Sample CLK Correlator I (8:1)/
Rate
CCK Magnitude
14
Correlator Q Sample CLK
Correlator Q
High Rate
(8:1)/CCK Quality
15
Chip Error
0
Chip Error Accum
Accumulator
(14:7)
16
NCO Test Hi Sample CLK NCO Accum (19:12)
Rate
17
Freq Test Hi Sample CLK Lag Accum (18:11)
Rate
18
Carrier Phase Sample CLK Carrier Phase Error
Error Hi Rate
(6,6:0)
19
Reserved Sample CLK Factory Test Only
20
Reserved Sample CLK Factory Test Only
21
I_A/D, Q_A/D Sample CLK 0,0,I_A/D (2:0),Q_A/D
(2:0)
22
Reserved
Reserved Factory Test Only
23
Reserved
Reserved Factory Test Only
24
Reserved
Reserved Factory Test Only
25 A/D Cal Accum A/D Cal A/D Cal Accum (7:0)
Lo
Accum (8)
26 A/D Cal Accum A/D Cal A/D Cal Accum (16:9)
Hi
Accum (17)
27 Freq Accum Lo Freq Accum Freq Accum (14:7)
(15)
28
Reserved
Reserved Factory Test Only
29 SQ2 Monitor Hi Pulse After
SQ Valid
SQ2 (15:8)
30-31
Reserved
Reserved Factory Test Only
Definitions
ED. Energy Detect, indicates that the RSSI value exceeds its
programmed threshold.
CRS. Carrier Sense, indicates that a signal has been
acquired (PN acquisition).
TXCLK. Transmit clock.
Track. Indicates start of tracking and start of SFD time-out.
SFD Detect. Variable time after track starts.
Signal Field Ready. ~ 8µs after SFD detect.
Length Field Ready. ~ 32µs after SFD detect.
Header CRC Valid. ~ 48µs after SFD detect.
DCLK. Data bit clock.
FrqReg. Contents of the NCO frequency register.
PhaseReg. Phase of signal after carrier loop correction.
NCO PhaseAccumReg. Contents of the NCO phase
accumulation register.
SQ1. Signal Quality measure #1. Contents of the bit sync
accumulator. Eight MSBs of most recent 16-bit stored value.
SQ2. Signal Quality measure #2. Signal phase variance
after removal of data. Eight MSBs of most recent 16-bit
stored value.
Sample CLK. Receive clock (RX sample clock). Nominally
22MHz.
Subsample CLK. LO rate symbol clock. Nominally 1MHz.
BitSyncAccum. Real time monitor of the bit synchronization
accumulator contents, mantissa only.
A/D_Cal_ck. Clock for applying A/D calibration corrections.
A/DCal. 5-bit value that drives the D/A adjusting the A/D
reference.
MODE
SLEEP
RX_PE
Inactive
TX_PE
Inactive
STANDBY Inactive Inactive
TX
Inactive
Active
RX
Active
Inactive
NO CLOCK
ICC Standby
TABLE 6. POWER DOWN MODES
RESET AT 44MHz
DEVICE STATE
Active
600µA
Both transmit and receive functions disabled. Device in sleep mode. Control
Interface is still active. Register values are maintained. Device will return to its
active state within 10µs plus settling time of AC coupling capacitors (about
5ms).
Inactive
7mA
Both transmit and receive operations disabled. Device will resume its
operational state within 1µs of RX_PE or TX_PE going active.
Inactive
10mA
Receiver operations disabled. Receiver will return in its operational state
within 1µs of RX_PE going active.
Inactive
29mA Transmitter operations disabled. Transmitter will return to its operational state
within 2 MCLKs of TX_PE going active.
Active
300µA All inputs at VCC or GND.
4-11
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