HFA3861B データシートの表示（PDF） - Intersil

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HFA3861B

Direct Sequence Spread Spectrum Baseband Processor

Intersil 

HFA3861B

For the 5.5Mbps CCK mode, the output of the scrambler is

partitioned into nibbles. The first two bits are encoded as

differential modulation in accordance with Table 5 . All odd

numbered symbols of the short Header or MPDU are given

an extra 180 degree (π) rotation in addition to the standard

DQPSK modulation as shown in the table. The symbols of

the MPDU shall be numbered starting with “0” for the first

symbol for the purposes of determining odd and even

symbols. That is, the MPDU starts on an even numbered

symbol. The last data dibits d2, and d3 CCK encode the

basic symbol as specified in Table 6. This table is derived

from the formula above by setting ϕ2 = (d2*pi)+ pi/2, ϕ3 = 0,

and ϕ4 = d3*pi. In the table d2 and d3 are in the order shown

and the complex chips are shown LSB to MSB (left to right)

with LSB transmitted first.

TABLE 5. DQPSK ENCODING TABLE

EVEN SYMBOLS ODD SYMBOLS

DIBIT PATTERN (d(0), d(1)) PHASE CHANGE PHASE CHANGE

d(0) IS FIRST IN TIME

(+jω)

(+jω)

00

0

π

01

π/2

3π/2 (-π/2)

11

π

0

10

3π/2 (-π/2)

π/2

TABLE 6. 5.5Mbps CCK ENCODING TABLE

d2, d3

00 : 1j

1

1j -1 1j

1 -1j 1

01 : -1j -1 -1j 1 1j 1 -1j 1

10 : -1j 1 -1j -1 -1j 1 1j 1

11 : 1j -1 1j 1 -1j 1 1j 1

At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted

per symbol.

The first dibit (d0, d1) encodes ϕ1 based on DQPSK. The

DQPSK encoder is specified in Table 6 above. The phase

change for ϕ1 is relative to the phase ϕ1 of the preceding

symbol. In the case of rate change, the phase change for ϕ1

is relative to the phase ϕ1 of the preceding CCK symbol. All

odd numbered symbols of the MPDU are given an extra 180

degree (π) rotation in accordance with the DQPSK

modulation as shown in Table 7. Symbol numbering starts

with “0” for the first symbol of the MPDU.

The data dibits: (d2, d3), (d4, d5), (d6, d7) encode ϕ2, ϕ3,

and ϕ4 respectively based on QPSK as specified in Table 7.

Note that this table is binary, not Grey, coded.

TABLE 7. QPSK ENCODING TABLE

DIBIT PATTERN (d(i), d(i+1))

d(i) IS FIRST IN TIME

PHASE

00

0

01

π/2

10

π

11

3π/2 (-π/2)

TX Power Control

The transmitter power can be controlled by the MAC via two

registers. The first register, CR58, contains the results of

power measurements digitized by the HFA3861B. By

comparing this measurement to what the MAC needs for

transmit power, the MAC can determine whether to raise or

lower the transmit power. It does this by writing the power

level desired to register CR31.

Clear Channel Assessment (CCA) and

Energy Detect (ED) Description

The clear channel assessment (CCA) circuit implements the

carrier sense portion of a carrier sense multiple access (CSMA)

networking scheme. The Clear Channel Assessment (CCA)

monitors the environment to determine when it is feasible to

transmit. The CCA circuit in the HFA3861B can be programmed

to be a function of RSSI (energy detected on the channel),

CS1, SQ1, or both. The CCA output can be ignored, allowing

transmissions independent of any channel conditions. The CCA

in combination with the visibility of the various internal

parameters (i.e., Energy Detection measurement results), can

assist an external processor in executing algorithms that can

adapt to the environment. These algorithms can increase

network throughput by minimizing collisions and reducing

transmissions liable to errors.

There are three measures that can be used in the CCA

assessment. The receive signal strength indication (RSSI)

which indicates the energy at the antenna, CS1 and carrier

sense (SQ1). SQ1 becomes active only when a spread

signal with the proper PN code has been detected, and the

peak correlation amplitude to sidelobe ratio exceeds a set

threshold, so it may not be adequate in itself.

CS1 becomes active anytime the AGC portion of the circuit

becomes unlocked, which is likely at the onset of a signal

that is strong enough to support 11Mbps, but may not occur

with the onset of a signal that is only strong enough to

support 1 or 2MBps. CS1 stays active until the AGC locks

and a SQ1 assessment is done, if SQ1 is false, then CS1 is

cleared, which deasserts CCA. If SQ1 is true, then tracking

is begun, and CCA continues to show the channel busy. CS1

may occur at any time during acquisition as the AGC state

machine runs asynchronously with respect to slot times.

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