HFA3860A データシートの表示（PDF） - Intersil

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HFA3860A

Direct Sequence Spread Spectrum Baseband

Intersil 

HFA3860A

SQ2. Signal Quality measure #2. Signal phase variance

after removal of data, Eight MSBs of most recent 16-bit

stored value.

Sample CLK. Receive clock (RX sample clock). Nominally

22MHz.

Subsample CLK. LO rate symbol clock. Nominally 1MHz.

BitSyncAccum. Real time monitor of the bit synchronization

accumulator contents, mantissa only.

A/D_Cal_ck. Clock for applying A/D calibration corrections.

A/DCal. 5-bit value that drives the D/A adjusting the A/D

reference.

MODE

SLEEP

RX_PE

Inactive

TX_PE

Inactive

STANDBY Inactive Inactive

TX

Inactive

Active

RX

Active

Inactive

NO CLOCK

ICC Standby

TABLE 6. POWER DOWN MODES

RESET AT 44MHz

DEVICE STATE

Active

4mA

Both transmit and receive functions disabled. Device in sleep mode. Control

Interface is still active. Register values are maintained. Device will return to its

active state within 10µs plus settling time of AC coupling capacitors (about

5µs).

Inactive

11mA

Both transmit and receive operations disabled. Device will resume its

operational state within 1µs of RX_PE or TX_PE going active.

Inactive

15mA

Receiver operations disabled. Receiver will return in its operational state

within 1µs of RX_PE going active.

Inactive

24mA Transmitter operations disabled. Transmitter will return to its operational state

within 2 MCLKs of TX_PE going active.

Active

300µA All inputs at VCC or GND.

Power Down Modes

The power consumption modes of the HFA3860A are

controlled by the following control signals.

Receiver Power Enable (RX_PE, pin 33), which disables the

receiver when inactive.

Transmitter Power Enable (TX_PE, pin 2), which disables the

transmitter when inactive.

Reset (RESET, pin 28), which puts the receiver in a sleep

mode. The power down mode where, both RESET and

RX_PE are used is the lowest possible power consumption

mode for the receiver. Exiting this mode requires a maximum

of 10µs before the device is back at its operational mode for

transmitters. Add 5µs more to be operational for receive

mode. It also requires that RX_PE be activated briefly to

clock in the change of state.

The contents of the Configuration Registers are not effected

by any of the power down modes. The external processor

does have access and can modify any of the CRs during the

power down modes. No reconfiguration is required when

returning to operational modes.

Table 6 describes the power down modes available for the

HFA3860A (VCC = 3.3V). The table values assume that all

other inputs to the part (MCLK, SCLK, etc.) continue to run

except as noted.

Transmitter Description

The HFA3860A transmitter is designed as a Direct

Sequence Spread Spectrum Phase Shift Keying (DSSS

PSK) modulator. It can handle data rates of up to 11MBPS

(refer to AC and DC specifications). The various modes of

the modulator are Differential Binary Phase Shift Keying

(DBPSK), Differential Quaternary Phase Shift Keying

(DQPSK), Binary M-ary Bi-Orthogonal Keying (BMBOK),

and Quaternary M-ary Bi-Orthogonal Keying (QMBOK).

These implement data rates of 1, 2, 5.5 and 11MBPS as

shown in Table 7. The major functional blocks of the

transmitter include a network processor interface, DPSK

modulator, high rate modulator, a data scrambler and a

spreader, as shown on Figure 8. A description of (M-ARY)

Bi-Orthogonal Keying can be found in Chapter 5 of:

“Telecommunications System Engineering”, by Lindsey and

Simon, Prentis Hall publishing.

The preamble and header are always transmitted as DBPSK

waveforms while the data packets can be configured to be

either DBPSK, DQPSK, BMBOK, or QMBOK. The preamble

is used by the receiver to achieve initial PN synchronization

while the header includes the necessary data fields of the

communications protocol to establish the physical layer link.

The transmitter generates the synchronization preamble and

header and knows when to make the DBPSK to DQPSK or

B/QMBOK switchover, as required.

For the PSK modes, the transmitter accepts data from the

external source, scrambles it, differentially encodes it as

either DBPSK or DQPSK, and mixes it with the BPSK PN

spreading. The baseband digital signals are then output to

the external IF modulator.

For the MBOK modes, the transmitter inputs the data and

forms it into nibbles (4 bits). At 5.5MBPS, it selects one of 8

spread sequences from a table of sequences with 3 of those

bits and then picks the true or inverted version of that

sequence with the remaining bit. Thus, there are 16 possible

spread sequences to send, but only one is sent. This

sequence is then modulated on both the I and Q outputs.

The phase of the last bit of the header is used as an

2-142

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