HFA3860A データシートの表示（PDF） - Intersil

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HFA3860A

Direct Sequence Spread Spectrum Baseband

Intersil 

HFA3860A

The interface specifications for the RSSI A/D are listed in

Table 4 below (VREFP = 1.75V).

TABLE 4. RSSI A/D SPECIFICATIONS

PARAMETER

MIN

TYP

Full Scale Input Voltage

-

-

Input Bandwidth (0.5dB)

1MHz

-

Input Capacitance

-

7pF

Input Impedance (DC)

1M

-

MAX

1.15

-

-

-

Test Port

The HFA3860A provides the capability to access a number of

internal signals and/or data through the Test port, pins TEST

7:0. In addition pin 1 (TEST_CK) is an output that can be used

in conjunction with the data coming from the test port outputs.

The test port is programmable through configuration register

(CR28). Any signal on the test port can also be read from

configuration register (CR29) via the serial control port.

There are 32 modes assigned to the PRISM test port. Some

are only applicable to factory test.

TABLE 5. TEST MODES

MODE DESCRIPTION

0 Quiet Test Bus

1 RX Acquisition

Monitor

2 TX Field Monitor

3 RSSI Monitor

4 SQ1 Monitor

5 SQ2 Monitor

6

7

8

9

10

(0Ah)

11

12

Correlator Lo

Rate

Freq Test Lo

Rate

Phase Test Lo

Rate

NCO Test Lo

Rate

Bit Sync Accum

Lo Rate

Reserved

A/D Cal Test

Mode

TEST_CLK

TEST (7:0)

0

00

Initial Detect

A/DCal, CRS, ED,

Track, SFD Detect, Sig-

nal Field Ready, Length

Field Ready, Header

CRC Valid

IQMARK

A/DCal, TXPE Internal,

Preamble Start, SFD

Start, Signal Field

Start, Length Field

Start, CRC Start,

MPDU Start

RSSI Pulse CSE Latched, CSE,

RSSI Out (5:0)

Pulse after SQ1 (7:0)

SQ is valid

Pulse after SQ2 (7:0)

SQ is valid

Sample CLK Correlator Magnitude

(7:0)

Subsample Frequency Register

CLK

(18:11)

Subsample Phase Register (7:3)

CLK

Shift <2:0>

Subsample NCO Register (15:8)

CLK

Enable

Bit Sync Accum (7:3)

Shift (2:0)

Reserved Factory Test Only

A/D Cal CLK A/DCal, ED, A/DCal

Disable, ADCal (4:0)

TABLE 5. TEST MODES (Continued)

MODE DESCRIPTION TEST_CLK

TEST (7:0)

13 Correlator I High Sample CLK Correlator I (8:1)

Rate

14 Correlator Q High Sample CLK Correlator Q (8:1)

Rate

15 Chip Error

0

Accumulator

Chip Error Accum

(14:7)

16 NCO Test Hi

Rate

Sample CLK NCO Accum (19:12)

17 Freq Test Hi Rate Sample CLK Lag Accum (18:11)

18 Carrier Phase

Error Hi Rate

Sample CLK Carrier Phase Error

(6,6:0)

19 Reserved

Sample CLK Factory Test Only

20 Reserved

Sample CLK Factory Test Only

21 I_A/D, Q_A/D

Sample CLK 0,0,I_A/D (2:0),Q_A/D

(2:0)

22 Reserved

Reserved Factory Test Only

23 Reserved

Reserved Factory Test Only

24 Reserved

Reserved Factory Test Only

25 A/D Cal Accum A/D Cal

Lo

Accum (8)

A/D Cal Accum (7:0)

26 A/D Cal Accum Hi A/D Cal

A/D Cal Accum (16:9)

Accum (17)

27 Freq Accum Lo Freq Accum Freq Accum (14:7)

(15)

28 Reserved

Reserved Factory Test Only

29 SQ2 Monitor Hi Pulse After SQ2 (15:8)

SQ Valid

30-31 Reserved

Reserved Factory Test Only

Definitions

ED. Energy Detect, indicates that the RSSI value exceeds its

programmed threshold.

CRS. Carrier Sense, indicates that a signal has been

acquired (PN acquisition).

TXCLK. Transmit clock.

Track. Indicates start of tracking and start of SFD time-out.

SFD Detect. Variable time after track starts.

Signal Field Ready. ~ 8µs after SFD detect.

Length Field Ready. ~ 32µs after SFD detect.

Header CRC Valid. ~ 48µs after SFD detect.

DCLK. Data bit clock.

FrqReg. Contents of the NCO frequency register.

PhaseReg. phase of signal after carrier loop correction.

NCO PhaseAccumReg. Contents of the NCO phase

accumulation register.

SQ1. Signal Quality measure #1. Contents of the bit sync

accumulator. Eight MSBs of most recent 16-bit stored value.

2-141

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