W83194BR-SD データシートの表示（PDF） - Winbond

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W83194BR-SD

Winbond Clock Generator For INTEL P4 Springdale Series Chipset

Winbond 

W83194BR-SD/W83194BG-SD

CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET

3. PIN CONFIGURATION

FS1*/REF0 1

FS0*/REF1 2

REF2 3

VDDREF 4

XIN 5

XOUT 6

GND 7

FS2&/PCICLK_F0 8

FS4&/PCICLK_F1 9

PCICLK_F2 10

VDDPCI 11

GND 12

PCICLK0 13

PCICLK1 14

PCICLK2 15

PCICLK3 16

VDDPCI 17

GND 18

PCICLK4 19

PCICLK5 20

SEL24_48#&/24_48MHz 21

FS3&/48MHz_USB 22

48MHz_DOT 23

GND 24

48 VDDA

47 GND

46 IREF

45 RESET#

44 GND

43 CPUCLKT1

42 CPUCLKC1

41 VDDCPU

40 CPUCLKT0

39 CPUCLKC0

38 GND

37 SRCCLKT

36 SRCCLKC

35 VDD

34 VTT_PWRGD/PD#*

33 SDATA*

32 SCLK*

31 3V66_0

30 3V66_1

29 GND

28 VDD3V66

27 3V66_2

26 3V66_3/VCH/VCH_EN&

25 VDD48

#: Active low

*: Internal pull up resistor 120KΩ to VDD

&: Internal Pull-down resistor 120KΩ to GND

4. BLOCK DIAGRAM

X IN

XOUT

VTT_PW RGD

F S < 0 :4 >

V C H _EN &

PD#&

SEL24_48#&

SDATA*

SCLK*

PLL2

XTAL

OSC

PLL1

S p read

S pectrum

V CO C LK

M /N /R atio

ROM

L atch

& PO R

D ivider

C ontrol

L ogic

& C onfig

R egister

I2 C

In te rfa c e

D ivider

3

48M H z_USB,

48M H z_DOT,

24_48M Hz

3

R E F 0:2

2 C PU C L K _T 0:1

C P U C L K _C 0:1

2

SRCCLKT

SRCCLKC

3V 66_3/V C H

3

3V 66_0:2

9 P C IC L K _0:5,

PC IC L K _F0:2

RESET#

R ref

-2-

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