W83194BR-SD データシートの表示（PDF） - Winbond

部品番号

コンポーネント説明

一致するリスト

W83194BR-SD

Winbond Clock Generator For INTEL P4 Springdale Series Chipset

Winbond 

W83194BR-SD/W83194BG-SD

CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET

Table of Contents-

1. GENERAL DESCRIPTION ......................................................................................................... 1

2. FEATURES ................................................................................................................................. 1

3. PIN CONFIGURATION ............................................................................................................... 2

4. BLOCK DIAGRAM ...................................................................................................................... 2

5. PIN DESCRIPTION..................................................................................................................... 3

5.1 Crystal I/O ....................................................................................................................... 3

5.2 CPU, SRC, 3V66, PCI Clock Outputs ............................................................................ 3

5.3 Fixed Frequency Outputs ............................................................................................... 4

5.4 I2C Control Interface....................................................................................................... 4

5.5 Output Control Pins ........................................................................................................ 5

5.6 Power an GND Pins........................................................................................................ 5

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 6

7.

I2C CONTROL AND STATUS REGISTERS............................................................................... 7

7.1 Register 0: Frequency Select (Default =10H)................................................................. 7

7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default = E3H) ........................ 7

7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default = FFH) .................................. 8

7.4 Register 3: PCI, 3V66 Clock (1 = Enable, 0 = Disable) (Default = EFH)........................ 8

7.5 Register 4: 24_48 MHz, REF Control (1 = Enable, 0 = Disable) (Default =FCH)........... 8

7.6 Register 5: Watchdog Control (Default = 00H) ............................................................... 9

7.7 Register 6: Watchdog Timer (Default =08H) ................................................................ 10

7.8 Register 7: Asynchronous Program (Default = 40H) .................................................... 10

7.9 Register 8: M/N Program (Default = 8AH) .................................................................... 10

7.10 Register 9: M/N Program (Default = CEH) ................................................................... 11

7.11 Register 10: M/N Program (Default = 13H) .................................................................. 11

7.12 Register 11: Spread Spectrum Programming (Default = 2FH)..................................... 11

7.13 Register 12: Divider Ratio (Default = C6H)................................................................... 12

7.14 Register 13: Control (Default = 0FH) ............................................................................ 12

7.15 Register 14: Control (Default = 27H) ............................................................................ 13

7.16 Register 15: Control (Default =3CH)............................................................................. 13

7.17 Register 16: Control (Default = 24H) ............................................................................ 13

7.18 Register 17: Slew Rate Control (Default = 00H)........................................................... 14

7.19 Register 18: Slew Rate Control (Default = 00H)........................................................... 14

7.20 Register 19: Control (Default = 0AH)............................................................................ 15

7.21 Register 20: Winbond Chip ID – Project Code (Ready Only) (Default = 47H) ............. 15

- II -

Share Link: