:H &RQQHFW 7HFKQRORJLHV ,QF
VT82C596B
DDRQ (Drive)
DDACK# (Host)
STOP (Host)
HDMARDY# (Host)
Data
TLI4
TZA4
CRC
TDVS4
TDVH4
Figure 11. UltraDMA-33 IDE Timing - Drive Terminating DMA Burst During Read Command
DDRQ (Drive)
DDACK# (Host)
STOP (Host)
DDMARDY# (Host)
HSTROBE (Host)
Data
TLI5A
TLI5B
TMLI5
CRC
TDVS5
TDVH5
Figure 12. UltraDMA-33 IDE Timing - Drive Terminating DMA Burst During Write Command
Revision 0.3 June 17, 1999
-87-
Electrical Specifications