VT82885 データシートの表示（PDF） - Unspecified
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VT82885 Datasheet PDF : 16 Pages
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VIA Technologies, Inc.
VT82885
Real Time Clock
E. Periodic Interrupt Flag (PF) bit is cleared
to zero.
F. The device is not accessible until
RESET# is returned high.
G. Alarm Interrupt Flag (AF) bit is cleared to
zero.
H. IRQ# pin is in the high impedence state.
I. Square Wave Output Enable (SQWE)
bit is cleared to zero.
J. Update Ended Interrupt Enable (UIE) is
cleared to zero.
In a typical application RESET# can be
connected to VCC. This connection will allow
the VT82885 to go in and out of power fail
without affecting any of the control registers.
ADDRESS MAP
The address map of the VT82885 is shown
in Figure 2. The address map consists of
114 bytes of user RAM, 10 bytes of RAM
that contain the RTC time, calendar and
alarm data, and four bytes which are used
for control and status. All 128 bytes can be
directly written or read except the following:
1. Registers C and D are read-only.
2. Bit 7 of Register A is read-only.
3. The high order bit of the seconds byte is
read-only.
The contents of four registers (A, B, C and
D) are described in the “Register” section.
FIGURE 2: ADDRESS MAP VT82885
0
00
14 Bytes
Clock and Control
Status Registers
13
OD
14
0E
114 Bytes
Storage
Registers
127
7F
Binary or BCD Input
0
SECONDS
00
1 SECONDS ALARM 01
2
MINUTES
02
3 MINUTES ALARM 03
4
HOURS
04
5 HOURS ALARM 05
6 DAY OF THE WEEK 06
7 DAY OF THE MONTH 07
8
MONTH
08
9
YEAR
09
10
REGISTER A
0A
11
REGISTER B
0B
12
REGISTER C
0C
13
REGISTER D
0D
TIME, CALENDAR AND ALARM
LOCATIONS
The time and calendar information is
obtained by reading the appropriate memory
bytes. The time, calendar and alarm are set
or initialized by writing the appropriate RAM
bytes. The contents of the ten time, calen-
dar and alarm bytes can be either Binary or
Binary-Coded Decimal (BCD) format. Be-
fore writing the internal time, calendar and
alarm registers, the SET bit in Register B
5
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