VSC8124 データシートの表示（PDF） - Vitesse Semiconductor

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VSC8124

2.488 Gb/s Quad Data Re-timer

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8124

2.488 Gb/s Quad

Data Re-timer

Figure 5: High Speed Data Output Termination - AC Coupled

AC Coupled

VCC

Quad data Re-timer

VCC

DOUT

50Ω 0.1 µF

Zo = 50Ω

50Ω

DOUTN 50Ω 0.1 µF

VCC

Zo = 50Ω

50Ω

VCC

VCC

Quad data Re-timer

DOUT

50Ω

DC Coupled

Zo = 50Ω

DOUTN 50Ω

VCC

Zo = 50Ω

50Ω

50Ω

Figure 6: REFCK Input Termination - AC Coupled

REFCK Driver

Quad data Re-timer

Zo = 50Ω

0.1 µF DI

50Ω

VTERM

50Ω

Zo = 50Ω

DIN

0.1 µF

Notes:

1) It is recommended that the VTERM pins from multiple inputs NOT be tied together, unless driven from a low impedance

supply.

2) The reference clock receivers have self-biased inputs.

3) For unused reference clock receivers, it is recommended to tie one side low by connecting a 1k Ohm resistor to Vee, and

letting the other side float.

G52271-0, Rev. 1.14

2/23/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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