VSC8124 データシートの表示（PDF） - Vitesse Semiconductor

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VSC8124

2.488 Gb/s Quad Data Re-timer

Vitesse Semiconductor 

2.488 Gb/s Quad

Data Re-timer

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8124

Re-timer Bypass

The serial data re-timer can be individually bypassed for data channels. This allows asynchronous data sig-

nals to pass through the part. The bypass function is controlled by the RTBYP[0:3] pins.

High Speed Interfaces

Figure 4: High Speed Data Input Termination- AC Coupled

Xpnt switch

Zo = 50Ω

Zo = 50Ω

Quad data Re-timer

0.1 µF DI

50Ω

VTERM

50Ω

DIN

0.1 µF

Notes:

1)It is recommended that VTERM pins from multiple inputs NOT be tied together, unless driven from a low impedance sup-

ply.

2) The high speed data receivers have self biased inputs.

3) For unused serial data receivers, it is recommended to tie one side low by connecting a 1k Ohm resistor to Vee and let-

ting the other side float.

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52271-0, Rev. 1.14

2/23/00

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