V827316K04SXTG-A1 データシートの表示（PDF） - Mosel Vitelic Corporation
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V827316K04SXTG-A1
Mosel Vitelic Corporation
V827316K04SXTG-A1 Datasheet PDF : 13 Pages
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MOSEL VITELIC
V827316K04S
AC Characteristics (cont.)
(PC1600)
(PC2100B) (PC2100A)
Parameter
Symbol Min Max Min Max Min Max Unit Note
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
tDQSQ
-
0.5
-
0.5
-
0.6 ns
tQH
tHPmin
-
tHPmin
-
tHPmin
-
ns
1
-0.75ns
-0.75ns
-0.75ns
Clock Half Period
tHP
tCH/L
-
tCH/L
-
tCH/L
-
ns
1
min
min
min
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Input Pulse Width
Write DQS High Level Width
Write DQS Low Level Width
CLK to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Power Down Exit Time
Exit Self Refresh to Non-Read Command
Exit Self Refresh to Read Command
Average Periodic Refresh Interval
tIS
tIH
tIS
tIH
tIPW
tDQSH
tDQSL
tDQSS
tDS
tDH
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
tPDEX
tXSNR
tXSRD
tREFI
0.9
0.9
1.0
1.0
2.2
0.4
0.4
0.75
0.5
0.5
1.75
0.9
0.4
0
0.25
0.4
2
10
75
200
-
-
0.9
-
1.1
-
ns 2,3,5,6
-
0.9
-
1.1
-
ns 2,3,5,6
-
1.0
-
1.1
-
ns 2,4,5,6
-
1.0
-
1.1
-
ns 2,4,5,6
-
2.2
-
-
-
ns
6
0.6
0.4
0.6
0.4
0.6 CLK
0.6
0.4
0.6
0.4
0.6 CLK
1.25 0.75 1.25 0.75 1.25 CLK
-
0.5
-
0.6
-
ns
7
-
0.5
-
0.6
-
ns
7
-
1.75
-
2
-
ns
1.1
0.9
1.1
0.9
1.1 CLK
0.6
0.4
0.6
0.4
0.6 CLK
-
0
-
0
- CLK
-
0.25
-
0.25
- CLK
0.6
0.4
0.6
0.4
0.6 CLK
-
2
-
2
- CLK
-
10
-
10
-
ns
-
75
-
80
-
ns
-
200
-
200
- CLK 8
15.6
-
15.6
-
15.6 us
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
V827316K04S Rev. 1.6 March 2002
9
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