UPD72871GM データシートの表示（PDF） - NEC => Renesas Technology

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UPD72871GM

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72870,72871

CONTENTS

1. PIN FUNCTIONS ................................................................................................................................... 13

1.1 PCI/Cardbus Interface Signals: (52 pins)..................................................................................... 13

1.2 Cable Interface Signals: (15 pins) ................................................................................................ 14

1.3 PHY Signals: (9 pins)..................................................................................................................... 15

1.4 PHY Control Signals: (5 pins) ....................................................................................................... 15

1.5 PCI/Cardbus Select Signals: (2 pins) ........................................................................................... 16

1.6 Serial ROM Interface Signals: (3 pins) ......................................................................................... 16

1.7 Miscellaneous Signals: (1 pin)...................................................................................................... 16

1.8 IC: ( 21 pins) ................................................................................................................................... 17

1.9 VDD ................................................................................................................................................... 17

1.10 GND ............................................................................................................................................... 17

2. PHY REGISTERS .................................................................................................................................. 18

2.1 Complete Structure for PHY Registers ........................................................................................ 18

2.2 Port Status Page (Page 000) ......................................................................................................... 21

2.3 Vendor ID Page (Page 001) ........................................................................................................... 22

3. CONFIGURATION REGISTERS........................................................................................................... 23

3.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) ........................................................ 23

3.1.1 Offset_00 Vendor ID Register............................................................................................................ 24

3.1.2 Offset_02 DeviceID Register ............................................................................................................. 24

3.1.3 Offset_04 Command Register ........................................................................................................... 24

3.1.4 Offset_06 Status Register.................................................................................................................. 25

3.1.5 Offset_08 Revision ID Register.......................................................................................................... 26

3.1.6 Offset_09 Class Code Register ......................................................................................................... 26

3.1.7 Offset_0C Cache Line Size Register ................................................................................................. 26

3.1.8 Offset_0D Latency Timer Register..................................................................................................... 26

3.1.9 Offset_0E Header Type Register....................................................................................................... 26

3.1.10 Offset_0F BIST Register................................................................................................................... 26

3.1.11 Offset_10 Base Address 0 Register................................................................................................. 27

3.1.12 Offset_20 Subsystem Vendor ID Register ....................................................................................... 27

3.1.13 Offset_22 Subsystem ID Register.................................................................................................... 27

3.1.14 Offset_30 Expansion Rom Base Address Register ......................................................................... 27

3.1.15 Offset_34 Cap_Ptr Register............................................................................................................. 27

3.1.16 Offset_3C Interrupt Line Register .................................................................................................... 28

3.1.17 Offset_3D Interrupt Pin Register...................................................................................................... 28

3.1.18 Offset_3E Min_Grant Register......................................................................................................... 28

3.1.19 Offset_3F Max Lat Register ............................................................................................................. 28

3.1.20 Offset_40 PCI_OHCI_Control Register ........................................................................................... 28

3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register .................................................................................. 29

3.1.22 Offset_62 Power Management Capabilities Register ...................................................................... 29

3.1.23 Offset_64 Power Management Control/Status Register .................................................................. 30

3.2 CardBus Mode Configuration Register ( CARD_ON=High ) ...................................................... 31

3.2.1 Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers)............................................ 32

3.2.2 Offset_28 Cardbus CIS Pointer ......................................................................................................... 33

3.2.3 Offset_80 CIS Area............................................................................................................................ 33

Preliminary Data Sheet S13925EJ2V0DS00

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