UPD72852A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72852A

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

NEC => Renesas Technology 

µPD72852A

3.1.5 LKON

When the Link power is off, it outputs a clock of 6.144 MHz. LKON outputs under the following conditions: LPS is

Low and the internal PHY register of the Link_active bit is 0.

• Link-on packet is received.

• Any bit of Loop, Pwr_fail, Timeout or Port_event is the PHY internal register becomes 1, and moreover either LPS

or Link_active bit is 0.

When LPS is asserted, LKON returns to Low.

3.1.6 DIRECT

Set DIRECT to Low for using the isolation barrier.

3.1.7 Isolation Barrier

The IEEE1394 cable holds signals for Data/Strobe in addition to power and ground.

When the ground potential is different between connecting devices, the DC and AC current flows through the

ground line in the cable and there is a possibility of malfunction due to ground difference between the two PHY.

The µPD72852A uses the isolation barrier to couple the AC between the PHY/Link interface to overcome the

ground difference problem. Connecting the DIRECT pin to Low enables the digital differential circuit of the

µPD72852A. The differential circuit propagates only the change in the signal; the interface will be driven only during

transitions High → Low or Low → High. The interface will assume the high impedance state when there is no signal

change. The µPD72852A uses Schmitt trigger input buffers for D, CTL, LREQ and LPS pins to prevent noise when the

bus assumes a high impedance state.

The digital differential circuit and the Schmitt trigger input buffers are needed on the Link layer controller LSI to

implement the isolation barrier.

Figure 3-2. Waveforms of the Isolation Barrier

011000100

01Z0ZZ10Z

Isolation Barrier not used

Using Isolation Barrier

(Digital differential circuit)

Data Sheet S16725EJ2V0DS

17

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