UPD72852A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72852A

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

NEC => Renesas Technology 

µPD72852A

Field

Long Debounce

W_SPD_DIS

Table 2-4. Bit Field Description

Size R/W Reset value

Description

2 R/W

00b

00: suspend debounce timer sets to 420 ns

11: suspend debounce timer sets to 1000 ns.

1 R/W

0

0: NOT Receive Double speed signal

Only First speed signal will be repeated for next port and packet will be

decoded by highest speed within received.

1: Receive Double speed signal (IEEE1394a-2000 complient).

Second speed signal will be applied for repeating /decoding.

2.5 Vendor Dependent Page (Page 111 : Port_select 0001)

Figure 2-5. Vendor Dependent Page contd.

0

1

2

3

4

5

6

7

1000

1001

1010

1011

1100

Reg_array

1101

1110

1111

Field

Reg_array

Table 2-5. Bit Field Description

Size R/W Reset value

Description

64 R/W

0

This register array is possible R/W.

Data Sheet S16725EJ2V0DS

15

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