UPD72873 データシートの表示（PDF） - NEC => Renesas Technology
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UPD72873 Datasheet PDF : 40 Pages
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µPD72873
(3) Function Reset Status Register (FRSR) (Base Address 1 (2) + 8H)
Bits
0
1
2
3
4
14-5
15
31-16
R/W
Description
R
Write Protect (No Use).
Read only as ‘0’
R
Ready Status (No Use).
Read only as ‘0’
R
Battery Voltage Detect 2 (No Use).
Read only as ‘0’
R
Battery Voltage Detect 1 (No Use).
Read only as ‘0’
R/W
General Wake Up Mask
R
Reserved. Read only as ‘0’
R/W
Interrupt
R
Reserved. Read only as ‘0’
(4) Function Force Event Register (FFER) (Base Address 1 (2) + CH)
Bits
0
1
2
3
4
14-5
15
31-16
R/W
Description
R
Write Protect (No Use).
Read only as ‘0’
R
Ready Status (No Use).
Read only as ‘0’
R
Battery Voltage Detect 2 (No Use).
Read only as ‘0’
R
Battery Voltage Detect 1 (No Use).
Read only as ‘0’
R/W
General Wake Up Mask
-
No Use
R/W
Interrupt
R
Reserved. Read only as ‘0’
3.2.2 Offset_28 Cardbus CIS Pointer
This register specifies start memory address of the Cardbus CIS Area.
Bits
31-0
R/W
R
Starting Pointer of CIS Area.
Constant value of 00000080H.
Description
3.2.3 Offset_80 CIS Area
The µPD72873 supports external Serial ROM (AT24C02 compatible) interface.
CIS Area Register can be loaded from external Serial ROM in the CIS area when CARD_ON is 1.
28
Preliminary Data Sheet S15305EJ2V0DS
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