UPD72873 データシートの表示（PDF） - NEC => Renesas Technology
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UPD72873 Datasheet PDF : 40 Pages
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µPD72873
3.1.16 Offset_3D Interrupt Pin Register
This register provides the interrupt line routing information specific to the µPD72873, the NEC’s implementation of
the 1394 OHCI specification.
Bits
7-0
R/W
Description
R
Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.
3.1.17 Offset_3E Min_Gnt Register
This register specifies how long of a burst period the µPD72873 needs, assuming a clock rate of 33 MHz.
Resolution is in units of ¼ µs. The value should be loaded into the register from the external serial EEPROM upon
power-up reset, and access to this register through PCI-bus is prohibited.
Bits
7-0
R/W
Description
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.18 Offset_3F Max_Lat Register
This register specifies how often the µPD72873 needs to gain access to the PCI-bus, assuming a clock rate of 33
MHz. Resolution is in units of ¼ µs. The value should be loaded into the register from the external serial EEPROM
after hardware reset, and access to this register through PCI-bus is prohibited.
Bits
7-0
R/W
Description
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.19 Offset_40 PCI_OHCI_Control Register
This register specifies the control bits that are IEEE1394 OHCI specific. Vendor options are not allowed in this
register. It is reserved for OHCI use only.
Bits
0
31-1
R/W
Description
R/W
PCI global SWAP Default value of 0. When this bit is 1, all quadrates read from and written to
the PCI Interface are byte swapped, thus a “PCI Global Swap”. PCI addresses for expansion
ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not
required for motherboard implementations.
R
Reserved Constant value of all 0.
3.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register
The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the
Next_Item_Ptr describes the location of the next item in the µPD72873’s Capability List.
Bits
7-0
15-8
R/W
Description
R
Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI
Power Management registers, while the ID value is assigned by the PCI SIG.
R
Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link
List.
Preliminary Data Sheet S15305EJ2V0DS
23
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