UPD6376CX データシートの表示（PDF） - NEC => Renesas Technology

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UPD6376CX

AUDIO 2-CHANNEL 16-BIT D/A CONVERTER

NEC => Renesas Technology 

µPD6376

2. INPUT SIGNAL FORMAT

• Input data must be input as 2’s complement, MSB first.

2’s complement is a method of expressing both positive numbers and negative numbers as binary numbers. See

the table below.

(MSB)

0111

0111

2’s Complement

1111

1111

1111

1111

Decimal Number

(LSB)

1111

+32767

1110

+32766

L.OUT, R.OUT Pin Voltage TYP. (V)

(Reference Values)Note

2.6

0000

0000

0000

0001

+1

0000

0000

0000

0000

0

1.6

1111

1111

1111

1111

–1

1000

0000

0000

0001

–32767

1000

0000

0000

0000

–32768

0.6

Note When A.VDD = 5.0 V

Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient temperature.

• Synchronize the (SI, LSI, RSI) data bit delimitations and the LRCK, WDCK reverse timing to the falling edge of

CLK.

• CLK requires the input of 16 clocks between sample data (16 bits). Also, make the time interval for 1 bit the same

as 1 clock cycle.

5

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