TIMING CHART 2
• When Pin 1 is High (parallel input)
4.5 clocks
CLK
LSB
LSI 16
LSB
RSI 16
WDCK
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
N
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
N
L.OUT
N–1
R.OUT
N–1
CLK
SI
Analog output update
tSCK
tSCK
tDC
tCD
CLK
WDCK
tDC
MSB
1 2 3 4 5 6 7 8 9 10 11
MSB
1 2 3 4 5 6 7 8 9 10 11
N+1
N
N
tCD