UPD161622 データシートの表示（PDF） - NEC => Renesas Technology
部品番号
コンポーネント説明
一致するリスト
UPD161622 Datasheet PDF : 103 Pages
| |||
µ PD161622
5. DESCRIPTION OF FUNCTIONS
5.1 CPU Interface
5.1.1 Selection of interface type
The µ PD161622 chip transfers data using a 16-bit bi-directional data bus (D15 to D0), 8-bit bi-directional data bus (D7
to D0) or a serial data input (SI). Setting the polarity of the PSX pin as either H or L enables the selections shown in
table 5–1 below.
Table 5–1.
PSX BMD
Mode
/CS
RS
/RD (E) /WR (R,/W) C86 D15 to D8 D7
D6 D5 to D0
H
0
16-bit parallel /CS
RS
/RD (E) /WR (R,/W) C86 D15 to D8 D7
D6 D5 to D0
H
1
8-bit parallel /CS
RS
/RD (E) /WR (R,/W)
C86
Hi-ZNote1
D7
D6 D5 to D0
L
X Note2
Serial Note3
/CS
RS
Note2
Note2
Note2 Hi-ZNote1
SI
SCL Hi-ZNote1
Notes 1. Hi-Z: High impedance
2. X: Don’t care (1 or 0)
3. In serial mode, read function is not available.
5.1.2 Parallel interface
When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct
connection to an i80 series or M68 series CPU (see table 5–2 below).
Table 5–2.
C86
Mode
/RD (E)
H
M68 series CPU
E
L
i80 series CPU
/RD
/WR (R,/W)
R, /W
/WR
The data bus signal is identified according to the combination of the RS, /RD (E), and /WR (R, /W) signals, as shown
in the following table 5–3.
Common
RS
H
H
L
L
M68 series CPU
R, /W
H
L
H
L
Table 5–3.
i80 series CPU
/RD
/WR
L
H
H
L
L
H
H
L
Function
Read display data and registers
Write display data and registers
Prohibited
Write to control index register
14
Data Sheet S15649EJ2V0DS
Share Link: 