UPD161620 データシートの表示（PDF） - NEC => Renesas Technology

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UPD161620

432 OUTPUT TFT-LCD SOURCE DRIVER WITH RAM

NEC => Renesas Technology 

µ PD161620

Symbol

5 RDY

5 D0 to D7

(SI)

(SO)

(SCL)

5 RS

TESTOUT

/RESET

5 TEST4,

TEST5

TEST2,

TEST3

5 IP0 to IP3

5 OP0 to OP3

5 TEST6

5 TEST1

5 TEST10

5 LPMG

5 LPMP

5 GOE1

5 GOE2

Pin Name

Ready signal

Pad No.

527

Data bus

(Serial data Input)

(Serial data output)

(Serial clock)

517 to 524

Index register/data, 516

command selection

Test output

506

Reset

526

Test

Input port

540,

541

545,

543

452 to 449

Output port

457 to 459

Test

479

547

441

Low power mode signal 442

501

OE1 output for gate 445

driver

OE2 output for gate 444

driver

(2/3)

I/O

Function

Output This pin is the ready signal output. When in 4-bit or 8-bit parallel mode,

connect this pin to external WAIT pin of the CPU. When in serial mode,

this pin is not used, so leave it open.

I/O These pins comprise 8-bit bi-directional data.

When the serial interface has been selected (PSX1 = L ), D7 functions as a

serial data input pin (SI), D6 functions as a serial clock input pin (SCL),

and D5 functions as a serial data output pin (SO). In either case, pins D0

to D4 are in high impedance mode.

When the chip is not selected, D0 to D7 are in high impedance mode.

Input When parallel data transfer has been selected, this pin is usually

connected to the LSB of the standard CPU address bus and is used to

distinguish between data from index registers and data/commands.

RS = H: Indicates that data from D0 to D7 is data/command

RS = L: Indicates that data from D0 to D7 is index register contents

Also, when serial data transfer is selected, the level of the RS pin is

fetched at the rising edge of the eighth clock of the serial clock and

whether the data is index register contents or data/command is

distinguished.

RS = H: Indicates that the data input to SI is data/command.

RS= L: Indicates that the data input to SI is index register contents.

Output This test output pin is used when the IC is in test mode, otherwise, it is left

unconnected.

Input When /RESET is low, an internal reset is performed. The reset operation

is executed at the /RESET signal level. Be sure to perform reset via this

pin at power application.

Input Input low level.

Input This is a general-purpose input port. The status of these pins (H or L) can

be read via a command.

Because this is CMOS input, do not leave these pins open.

Output This is a general-purpose output port. The status of these pins (H or L)

can be write via a command.

Output Leave open.

Connect this pin to the SB pin of the gate driver.

Output This is an output pin for low power mode (for the gate driver).

Connect this pin to the LPM pin of the gate driver.

This is an output pin for the low power mode (for the power-supply IC).

Connect this pin to the LPM pin of the power-supply IC.

Output This pin is an output pin for the low power mode (for the OE1).

Connect to the OE1 pin of the gate driver.

For the signal output timing, refer to 5.4 Display Timing Generator.

Output This pin is the OE2 output for the gate driver.

Connect to the OE2 pin of the gate driver.

For the signal output timing, refer to 5.4 Display Timing Generator.

Preliminary Product Information S14797EJ3V7PM

9

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