SM8750AV データシートの表示（PDF） - Nippon Precision Circuits
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SM8750AV Datasheet PDF : 10 Pages
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SM8750AV
FUNCTIONAL DESCRIPTION
Serial Interface
The SM8750AV has a dedicated serial interface port
over which data can be written and the various oper-
ating modes can be controlled. The port address and
bit configuration are shown in table 1, and the data
bits are described in table 2.
Table 1. Port address and bit configuration
Bit number
15
(msb)
14
13
12
11
10
9
8
7
Data
TEST1 TEST0 CSDIS CS SP POLAR GMES FCG ×
6
5
4
3
2
1
0
(lsb)
Address
LOW HIGH HIGH HIGH HIGH HIGH ×
×: Don’t care.
Table 2. Data bit description
Bit
TEST[1:0]
CSDIS
CS
SP
POLAR
GMES
FCG
Description
Test mode setting
Auto-adjust disable
Auto-adjust start
Sleep mode settings
D ATA edge settings for phase measurement
Polarity setting for converter coefficient measurement
Converter coefficient measurement mode setting
RDCLK pulsewidth auto-adjust mode
Phase difference to voltage converter coefficient switching
LOW:LOW
LOW
LOW
LOW
LOW
LOW
LOW
Default
(normal operation)
(enabled)
(wait)
(normal operation)
(falling edge)
(1T discharge)
(normal operation)
(minimum pulsewidth)
(maximum converter coefficient)
Table 3. GMES and POLAR operating modes
GMES
LOW
LOW
HIGH
HIGH
POLAR
LOW
HIGH
LOW
HIGH
Operating mode
D ATA signal falling edge and RDCLK rising edge phase difference conversion
D ATA signal rising edge and RDCLK rising edge phase difference conversion
Output converter voltage for phase difference equivalent to −0.5T
Output converter voltage for phase difference equivalent to +0.5T
Serial data comprising 16 bits is input with the LSB
first. Valid data is read in on the 16th rising edge of
the SCLK input. On the next SCLK falling edge, the
SDATA N-channel open drain is turned ON and
SDATA goes LOW, performing the function of an
acknowledge signal.
If 15 or less SCLK rising edge pulses occur during
the interval when SENB is HIGH, the data received
up to the point when SENB goes LOW is ignored
and the internal port data is not updated. If 17 or
more SCLK rising edge pulses occur, the received
data is latched in the internal port on the 16th rising
edge and the acknowledge signal is output on the
next falling edge. The acknowledge signal is held
constant until SENB goes LOW again.
NIPPON PRECISION CIRCUITS—6
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