UBA2070 データシートの表示（PDF） - Philips Electronics
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UBA2070 Datasheet PDF : 20 Pages
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Philips Semiconductors
600 V CCFL ballast driver IC
Product specification
UBA2070
Power-down state
The Power-down state will be entered if, at the end of the
ignition time, the voltage at pin LVS is above VLVS(fail).
In the Power-down state the oscillation will be stopped and
MOSFETs Ths and Tls will be non-conductive. The VDD
supply is internally clamped. The circuit is released from
the Power-down state by reducing the supply voltage to
below VDD(reset).
Capacitive mode protection
The signal across RACM also gives information about the
switching behaviour of the half bridge. If the voltage at
RACM does not exceed the VCMD level during the
non-overlap time (see Fig.4), the Capacitive Mode
Detection (CMD) circuit assumes that the circuit is in
capacitive mode of operation. Consequently the frequency
will be directly increased to fmax. In this event the
frequency behaviour is decoupled from the voltage at
pin CSW until the voltage is discharged to zero. An internal
filter of 30 ns is included at pin ACM to increase the noise
immunity.
Charge coupling
Due to parasitic capacitive coupling to the high voltage
circuitry all pins are charged with a repetitive charge
injection. Given the typical application the pins
IREF and CF are sensitive to this charge injection. For
charge coupling of ±8 pC, a safe functional operation of
the IC is guaranteed, independent of the current level.
Charge coupling at current levels below 50 µA will not
interfere with the accuracy of the VCS and VACM levels.
Charge coupling at current levels below 20 µA will not
interfere with the accuracy of any parameter.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages referenced to ground.
SYMBOL
PARAMETER
Vhs
high side supply voltage
VACM
VLVS
VCS+
VCS−
VCSW
Tamb
Tj
Tstg
Vesd
voltage on pin ACM
voltage on pin LVS
voltage on pin CS+
voltage on pin CS−
voltage on pin CSW
ambient temperature
junction temperature
storage temperature
electrostatic discharge voltage
pins FVDD, GH, SH and VDD
pins GL, ACM, CS+, CS−, CSW,
LVS, CF, IREF, CT and VREF
CONDITION
Ihs < 30 µA; t < 1 s
Ihs < 30 µA
note 1
MIN.
−
−
−5
0
0
−0.3
0
−25
−25
−55
MAX.
600
510
+5
5
5
+5
5
+80
+150
+150
UNIT
V
V
V
V
V
V
V
°C
°C
°C
−1000 +1000 V
−2500 +2500 V
Note
1. In accordance with the human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series
resistor.
2002 Oct 24
9
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